171 lines
4.0 KiB
Plaintext
171 lines
4.0 KiB
Plaintext
/*
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* Copyright (c) 2013-2014 Linaro Ltd.
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* Copyright (c) 2013-2014 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/hix5hd2-clock.h>
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/ {
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aliases {
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serial0 = &uart0;
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};
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gic: interrupt-controller@f8a01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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/* gic dist base, gic cpu base */
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reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0 0xf8000000 0x8000000>;
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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ranges;
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timer0: timer@00002000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x00002000 0x1000>;
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/* timer00 & timer01 */
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interrupts = <0 24 4>;
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clocks = <&clock HIX5HD2_FIXED_24M>;
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status = "disabled";
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};
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timer1: timer@00a29000 {
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/*
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* Only used in NORMAL state, not available ins
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* SLOW or DOZE state.
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* The rate is fixed in 24MHz.
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*/
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x00a29000 0x1000>;
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/* timer10 & timer11 */
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interrupts = <0 25 4>;
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clocks = <&clock HIX5HD2_FIXED_24M>;
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status = "disabled";
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};
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timer2: timer@00a2a000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x00a2a000 0x1000>;
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/* timer20 & timer21 */
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interrupts = <0 26 4>;
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clocks = <&clock HIX5HD2_FIXED_24M>;
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status = "disabled";
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};
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timer3: timer@00a2b000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x00a2b000 0x1000>;
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/* timer30 & timer31 */
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interrupts = <0 27 4>;
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clocks = <&clock HIX5HD2_FIXED_24M>;
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status = "disabled";
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};
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timer4: timer@00a81000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x00a81000 0x1000>;
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/* timer30 & timer31 */
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interrupts = <0 28 4>;
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clocks = <&clock HIX5HD2_FIXED_24M>;
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status = "disabled";
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};
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uart0: uart@00b00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x00b00000 0x1000>;
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interrupts = <0 49 4>;
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clocks = <&clock HIX5HD2_FIXED_83M>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart1: uart@00006000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x00006000 0x1000>;
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interrupts = <0 50 4>;
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clocks = <&clock HIX5HD2_FIXED_83M>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart2: uart@00b02000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x00b02000 0x1000>;
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interrupts = <0 51 4>;
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clocks = <&clock HIX5HD2_FIXED_83M>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart3: uart@00b03000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x00b03000 0x1000>;
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interrupts = <0 52 4>;
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clocks = <&clock HIX5HD2_FIXED_83M>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart4: uart@00b04000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb04000 0x1000>;
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interrupts = <0 53 4>;
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clocks = <&clock HIX5HD2_FIXED_83M>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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};
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local_timer@00a00600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x00a00600 0x20>;
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interrupts = <1 13 0xf01>;
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};
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l2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x00a10000 0x100000>;
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interrupts = <0 15 4>;
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cache-unified;
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cache-level = <2>;
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};
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sysctrl: system-controller@00000000 {
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compatible = "hisilicon,sysctrl";
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reg = <0x00000000 0x1000>;
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reboot-offset = <0x4>;
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};
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cpuctrl@00a22000 {
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compatible = "hisilicon,cpuctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00a22000 0x2000>;
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ranges = <0 0x00a22000 0x2000>;
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clock: clock@0 {
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compatible = "hisilicon,hix5hd2-clock";
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reg = <0 0x2000>;
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#clock-cells = <1>;
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};
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};
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};
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};
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