657 lines
15 KiB
C
657 lines
15 KiB
C
/*
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* linux/drivers/video/amba-clcd.c
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*
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* Copyright (C) 2001 ARM Limited, by David A Rusling
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* Updated to 2.5, Deep Blue Solutions Ltd.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*
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* ARM PrimeCell PL110 Color LCD Controller
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*/
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/list.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/clk.h>
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#include <linux/hardirq.h>
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#include <asm/sizes.h>
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#define to_clcd(info) container_of(info, struct clcd_fb, fb)
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/* This is limited to 16 characters when displayed by X startup */
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static const char *clcd_name = "CLCD FB";
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/*
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* Unfortunately, the enable/disable functions may be called either from
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* process or IRQ context, and we _need_ to delay. This is _not_ good.
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*/
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static inline void clcdfb_sleep(unsigned int ms)
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{
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if (in_atomic()) {
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mdelay(ms);
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} else {
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msleep(ms);
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}
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}
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static inline void clcdfb_set_start(struct clcd_fb *fb)
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{
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unsigned long ustart = fb->fb.fix.smem_start;
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unsigned long lstart;
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ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
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lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
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writel(ustart, fb->regs + CLCD_UBAS);
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writel(lstart, fb->regs + CLCD_LBAS);
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}
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static void clcdfb_disable(struct clcd_fb *fb)
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{
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u32 val;
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if (fb->board->disable)
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fb->board->disable(fb);
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val = readl(fb->regs + fb->off_cntl);
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if (val & CNTL_LCDPWR) {
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val &= ~CNTL_LCDPWR;
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writel(val, fb->regs + fb->off_cntl);
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clcdfb_sleep(20);
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}
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if (val & CNTL_LCDEN) {
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val &= ~CNTL_LCDEN;
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writel(val, fb->regs + fb->off_cntl);
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}
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/*
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* Disable CLCD clock source.
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*/
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if (fb->clk_enabled) {
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fb->clk_enabled = false;
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clk_disable(fb->clk);
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}
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}
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static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
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{
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/*
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* Enable the CLCD clock source.
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*/
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if (!fb->clk_enabled) {
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fb->clk_enabled = true;
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clk_enable(fb->clk);
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}
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/*
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* Bring up by first enabling..
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*/
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cntl |= CNTL_LCDEN;
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writel(cntl, fb->regs + fb->off_cntl);
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clcdfb_sleep(20);
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/*
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* and now apply power.
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*/
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cntl |= CNTL_LCDPWR;
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writel(cntl, fb->regs + fb->off_cntl);
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/*
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* finally, enable the interface.
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*/
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if (fb->board->enable)
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fb->board->enable(fb);
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}
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static int
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clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
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{
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u32 caps;
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int ret = 0;
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if (fb->panel->caps && fb->board->caps)
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caps = fb->panel->caps & fb->board->caps;
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else {
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/* Old way of specifying what can be used */
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caps = fb->panel->cntl & CNTL_BGR ?
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CLCD_CAP_BGR : CLCD_CAP_RGB;
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/* But mask out 444 modes as they weren't supported */
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caps &= ~CLCD_CAP_444;
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}
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/* Only TFT panels can do RGB888/BGR888 */
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if (!(fb->panel->cntl & CNTL_LCDTFT))
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caps &= ~CLCD_CAP_888;
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memset(&var->transp, 0, sizeof(var->transp));
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var->red.msb_right = 0;
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var->green.msb_right = 0;
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var->blue.msb_right = 0;
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switch (var->bits_per_pixel) {
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case 1:
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case 2:
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case 4:
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case 8:
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/* If we can't do 5551, reject */
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caps &= CLCD_CAP_5551;
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if (!caps) {
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ret = -EINVAL;
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break;
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}
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var->red.length = var->bits_per_pixel;
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var->red.offset = 0;
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var->green.length = var->bits_per_pixel;
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var->green.offset = 0;
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var->blue.length = var->bits_per_pixel;
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var->blue.offset = 0;
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break;
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case 16:
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/* If we can't do 444, 5551 or 565, reject */
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if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
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ret = -EINVAL;
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break;
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}
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/*
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* Green length can be 4, 5 or 6 depending whether
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* we're operating in 444, 5551 or 565 mode.
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*/
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if (var->green.length == 4 && caps & CLCD_CAP_444)
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caps &= CLCD_CAP_444;
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if (var->green.length == 5 && caps & CLCD_CAP_5551)
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caps &= CLCD_CAP_5551;
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else if (var->green.length == 6 && caps & CLCD_CAP_565)
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caps &= CLCD_CAP_565;
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else {
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/*
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* PL110 officially only supports RGB555,
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* but may be wired up to allow RGB565.
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*/
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if (caps & CLCD_CAP_565) {
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var->green.length = 6;
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caps &= CLCD_CAP_565;
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} else if (caps & CLCD_CAP_5551) {
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var->green.length = 5;
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caps &= CLCD_CAP_5551;
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} else {
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var->green.length = 4;
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caps &= CLCD_CAP_444;
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}
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}
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if (var->green.length >= 5) {
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var->red.length = 5;
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var->blue.length = 5;
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} else {
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var->red.length = 4;
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var->blue.length = 4;
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}
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break;
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case 32:
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/* If we can't do 888, reject */
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caps &= CLCD_CAP_888;
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if (!caps) {
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ret = -EINVAL;
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break;
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}
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var->red.length = 8;
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var->green.length = 8;
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var->blue.length = 8;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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/*
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* >= 16bpp displays have separate colour component bitfields
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* encoded in the pixel data. Calculate their position from
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* the bitfield length defined above.
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*/
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if (ret == 0 && var->bits_per_pixel >= 16) {
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bool bgr, rgb;
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bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
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rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
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if (!bgr && !rgb)
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/*
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* The requested format was not possible, try just
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* our capabilities. One of BGR or RGB must be
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* supported.
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*/
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bgr = caps & CLCD_CAP_BGR;
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if (bgr) {
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var->blue.offset = 0;
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var->green.offset = var->blue.offset + var->blue.length;
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var->red.offset = var->green.offset + var->green.length;
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} else {
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var->red.offset = 0;
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var->green.offset = var->red.offset + var->red.length;
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var->blue.offset = var->green.offset + var->green.length;
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}
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}
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return ret;
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}
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static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
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{
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struct clcd_fb *fb = to_clcd(info);
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int ret = -EINVAL;
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if (fb->board->check)
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ret = fb->board->check(fb, var);
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if (ret == 0 &&
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var->xres_virtual * var->bits_per_pixel / 8 *
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var->yres_virtual > fb->fb.fix.smem_len)
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ret = -EINVAL;
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if (ret == 0)
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ret = clcdfb_set_bitfields(fb, var);
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return ret;
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}
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static int clcdfb_set_par(struct fb_info *info)
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{
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struct clcd_fb *fb = to_clcd(info);
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struct clcd_regs regs;
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fb->fb.fix.line_length = fb->fb.var.xres_virtual *
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fb->fb.var.bits_per_pixel / 8;
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if (fb->fb.var.bits_per_pixel <= 8)
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fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
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else
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fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
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fb->board->decode(fb, ®s);
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clcdfb_disable(fb);
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writel(regs.tim0, fb->regs + CLCD_TIM0);
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writel(regs.tim1, fb->regs + CLCD_TIM1);
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writel(regs.tim2, fb->regs + CLCD_TIM2);
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writel(regs.tim3, fb->regs + CLCD_TIM3);
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clcdfb_set_start(fb);
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clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
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fb->clcd_cntl = regs.cntl;
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clcdfb_enable(fb, regs.cntl);
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#ifdef DEBUG
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printk(KERN_INFO
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"CLCD: Registers set to\n"
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" %08x %08x %08x %08x\n"
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" %08x %08x %08x %08x\n",
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readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
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readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
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readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
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readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
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#endif
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return 0;
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}
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static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
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{
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unsigned int mask = (1 << bf->length) - 1;
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return (val >> (16 - bf->length) & mask) << bf->offset;
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}
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/*
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* Set a single color register. The values supplied have a 16 bit
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* magnitude. Return != 0 for invalid regno.
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*/
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static int
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clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
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unsigned int blue, unsigned int transp, struct fb_info *info)
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{
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struct clcd_fb *fb = to_clcd(info);
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if (regno < 16)
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fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
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convert_bitfield(blue, &fb->fb.var.blue) |
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convert_bitfield(green, &fb->fb.var.green) |
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convert_bitfield(red, &fb->fb.var.red);
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if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
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int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
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u32 val, mask, newval;
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newval = (red >> 11) & 0x001f;
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newval |= (green >> 6) & 0x03e0;
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newval |= (blue >> 1) & 0x7c00;
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/*
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* 3.2.11: if we're configured for big endian
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* byte order, the palette entries are swapped.
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*/
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if (fb->clcd_cntl & CNTL_BEBO)
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regno ^= 1;
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if (regno & 1) {
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newval <<= 16;
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mask = 0x0000ffff;
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} else {
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mask = 0xffff0000;
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}
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val = readl(fb->regs + hw_reg) & mask;
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writel(val | newval, fb->regs + hw_reg);
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}
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return regno > 255;
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}
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/*
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* Blank the screen if blank_mode != 0, else unblank. If blank == NULL
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* then the caller blanks by setting the CLUT (Color Look Up Table) to all
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* black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
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* to e.g. a video mode which doesn't support it. Implements VESA suspend
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* and powerdown modes on hardware that supports disabling hsync/vsync:
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* blank_mode == 2: suspend vsync
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* blank_mode == 3: suspend hsync
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* blank_mode == 4: powerdown
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*/
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static int clcdfb_blank(int blank_mode, struct fb_info *info)
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{
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struct clcd_fb *fb = to_clcd(info);
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if (blank_mode != 0) {
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clcdfb_disable(fb);
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} else {
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clcdfb_enable(fb, fb->clcd_cntl);
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}
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return 0;
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}
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static int clcdfb_mmap(struct fb_info *info,
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struct vm_area_struct *vma)
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{
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struct clcd_fb *fb = to_clcd(info);
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unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
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int ret = -EINVAL;
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len = info->fix.smem_len;
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if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
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fb->board->mmap)
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ret = fb->board->mmap(fb, vma);
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return ret;
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}
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static struct fb_ops clcdfb_ops = {
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.owner = THIS_MODULE,
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.fb_check_var = clcdfb_check_var,
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.fb_set_par = clcdfb_set_par,
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.fb_setcolreg = clcdfb_setcolreg,
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.fb_blank = clcdfb_blank,
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.fb_fillrect = cfb_fillrect,
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.fb_copyarea = cfb_copyarea,
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.fb_imageblit = cfb_imageblit,
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.fb_mmap = clcdfb_mmap,
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};
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static int clcdfb_register(struct clcd_fb *fb)
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{
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int ret;
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/*
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* ARM PL111 always has IENB at 0x1c; it's only PL110
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* which is reversed on some platforms.
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*/
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if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
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fb->off_ienb = CLCD_PL111_IENB;
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fb->off_cntl = CLCD_PL111_CNTL;
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} else {
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#ifdef CONFIG_ARCH_VERSATILE
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fb->off_ienb = CLCD_PL111_IENB;
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fb->off_cntl = CLCD_PL111_CNTL;
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#else
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fb->off_ienb = CLCD_PL110_IENB;
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fb->off_cntl = CLCD_PL110_CNTL;
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#endif
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}
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fb->clk = clk_get(&fb->dev->dev, NULL);
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if (IS_ERR(fb->clk)) {
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ret = PTR_ERR(fb->clk);
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goto out;
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}
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ret = clk_prepare(fb->clk);
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if (ret)
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goto free_clk;
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fb->fb.device = &fb->dev->dev;
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fb->fb.fix.mmio_start = fb->dev->res.start;
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fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
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fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
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if (!fb->regs) {
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printk(KERN_ERR "CLCD: unable to remap registers\n");
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ret = -ENOMEM;
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goto clk_unprep;
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}
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fb->fb.fbops = &clcdfb_ops;
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fb->fb.flags = FBINFO_FLAG_DEFAULT;
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fb->fb.pseudo_palette = fb->cmap;
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strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
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fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
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fb->fb.fix.type_aux = 0;
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fb->fb.fix.xpanstep = 0;
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fb->fb.fix.ypanstep = 0;
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fb->fb.fix.ywrapstep = 0;
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fb->fb.fix.accel = FB_ACCEL_NONE;
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fb->fb.var.xres = fb->panel->mode.xres;
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fb->fb.var.yres = fb->panel->mode.yres;
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fb->fb.var.xres_virtual = fb->panel->mode.xres;
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fb->fb.var.yres_virtual = fb->panel->mode.yres;
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fb->fb.var.bits_per_pixel = fb->panel->bpp;
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fb->fb.var.grayscale = fb->panel->grayscale;
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fb->fb.var.pixclock = fb->panel->mode.pixclock;
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fb->fb.var.left_margin = fb->panel->mode.left_margin;
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fb->fb.var.right_margin = fb->panel->mode.right_margin;
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fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
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fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
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fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
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fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
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fb->fb.var.sync = fb->panel->mode.sync;
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fb->fb.var.vmode = fb->panel->mode.vmode;
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fb->fb.var.activate = FB_ACTIVATE_NOW;
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fb->fb.var.nonstd = 0;
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fb->fb.var.height = fb->panel->height;
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fb->fb.var.width = fb->panel->width;
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fb->fb.var.accel_flags = 0;
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fb->fb.monspecs.hfmin = 0;
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fb->fb.monspecs.hfmax = 100000;
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fb->fb.monspecs.vfmin = 0;
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fb->fb.monspecs.vfmax = 400;
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fb->fb.monspecs.dclkmin = 1000000;
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fb->fb.monspecs.dclkmax = 100000000;
|
|
|
|
/*
|
|
* Make sure that the bitfields are set appropriately.
|
|
*/
|
|
clcdfb_set_bitfields(fb, &fb->fb.var);
|
|
|
|
/*
|
|
* Allocate colourmap.
|
|
*/
|
|
ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
|
|
if (ret)
|
|
goto unmap;
|
|
|
|
/*
|
|
* Ensure interrupts are disabled.
|
|
*/
|
|
writel(0, fb->regs + fb->off_ienb);
|
|
|
|
fb_set_var(&fb->fb, &fb->fb.var);
|
|
|
|
dev_info(&fb->dev->dev, "%s hardware, %s display\n",
|
|
fb->board->name, fb->panel->mode.name);
|
|
|
|
ret = register_framebuffer(&fb->fb);
|
|
if (ret == 0)
|
|
goto out;
|
|
|
|
printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
|
|
|
|
fb_dealloc_cmap(&fb->fb.cmap);
|
|
unmap:
|
|
iounmap(fb->regs);
|
|
clk_unprep:
|
|
clk_unprepare(fb->clk);
|
|
free_clk:
|
|
clk_put(fb->clk);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
|
|
{
|
|
struct clcd_board *board = dev_get_platdata(&dev->dev);
|
|
struct clcd_fb *fb;
|
|
int ret;
|
|
|
|
if (!board)
|
|
return -EINVAL;
|
|
|
|
ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = amba_request_regions(dev, NULL);
|
|
if (ret) {
|
|
printk(KERN_ERR "CLCD: unable to reserve regs region\n");
|
|
goto out;
|
|
}
|
|
|
|
fb = kzalloc(sizeof(struct clcd_fb), GFP_KERNEL);
|
|
if (!fb) {
|
|
printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
|
|
ret = -ENOMEM;
|
|
goto free_region;
|
|
}
|
|
|
|
fb->dev = dev;
|
|
fb->board = board;
|
|
|
|
dev_info(&fb->dev->dev, "PL%03x rev%u at 0x%08llx\n",
|
|
amba_part(dev), amba_rev(dev),
|
|
(unsigned long long)dev->res.start);
|
|
|
|
ret = fb->board->setup(fb);
|
|
if (ret)
|
|
goto free_fb;
|
|
|
|
ret = clcdfb_register(fb);
|
|
if (ret == 0) {
|
|
amba_set_drvdata(dev, fb);
|
|
goto out;
|
|
}
|
|
|
|
fb->board->remove(fb);
|
|
free_fb:
|
|
kfree(fb);
|
|
free_region:
|
|
amba_release_regions(dev);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int clcdfb_remove(struct amba_device *dev)
|
|
{
|
|
struct clcd_fb *fb = amba_get_drvdata(dev);
|
|
|
|
clcdfb_disable(fb);
|
|
unregister_framebuffer(&fb->fb);
|
|
if (fb->fb.cmap.len)
|
|
fb_dealloc_cmap(&fb->fb.cmap);
|
|
iounmap(fb->regs);
|
|
clk_unprepare(fb->clk);
|
|
clk_put(fb->clk);
|
|
|
|
fb->board->remove(fb);
|
|
|
|
kfree(fb);
|
|
|
|
amba_release_regions(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct amba_id clcdfb_id_table[] = {
|
|
{
|
|
.id = 0x00041110,
|
|
.mask = 0x000ffffe,
|
|
},
|
|
{ 0, 0 },
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
|
|
|
|
static struct amba_driver clcd_driver = {
|
|
.drv = {
|
|
.name = "clcd-pl11x",
|
|
},
|
|
.probe = clcdfb_probe,
|
|
.remove = clcdfb_remove,
|
|
.id_table = clcdfb_id_table,
|
|
};
|
|
|
|
static int __init amba_clcdfb_init(void)
|
|
{
|
|
if (fb_get_options("ambafb", NULL))
|
|
return -ENODEV;
|
|
|
|
return amba_driver_register(&clcd_driver);
|
|
}
|
|
|
|
module_init(amba_clcdfb_init);
|
|
|
|
static void __exit amba_clcdfb_exit(void)
|
|
{
|
|
amba_driver_unregister(&clcd_driver);
|
|
}
|
|
|
|
module_exit(amba_clcdfb_exit);
|
|
|
|
MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
|
|
MODULE_LICENSE("GPL");
|