143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2016 AmLogic, Inc.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* Copyright (c) 2017 Amlogic, inc.
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* Author: Qiufang Dai <qiufang.dai@amlogic.com>
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*
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*/
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#ifndef __AXG_H
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#define __AXG_H
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/*
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* Clock controller register offsets
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*
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* Register offsets from the data sheet must be multiplied by 4 before
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* adding them to the base address to get the right value.
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*/
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#define HHI_MIPI_CNTL0 0x00
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#define HHI_GP0_PLL_CNTL 0x40
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#define HHI_GP0_PLL_CNTL2 0x44
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#define HHI_GP0_PLL_CNTL3 0x48
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#define HHI_GP0_PLL_CNTL4 0x4c
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#define HHI_GP0_PLL_CNTL5 0x50
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#define HHI_GP0_PLL_STS 0x54
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#define HHI_GP0_PLL_CNTL1 0x58
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#define HHI_HIFI_PLL_CNTL 0x80
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#define HHI_HIFI_PLL_CNTL2 0x84
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#define HHI_HIFI_PLL_CNTL3 0x88
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#define HHI_HIFI_PLL_CNTL4 0x8C
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#define HHI_HIFI_PLL_CNTL5 0x90
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#define HHI_HIFI_PLL_STS 0x94
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#define HHI_HIFI_PLL_CNTL1 0x98
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#define HHI_XTAL_DIVN_CNTL 0xbc
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#define HHI_GCLK2_MPEG0 0xc0
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#define HHI_GCLK2_MPEG1 0xc4
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#define HHI_GCLK2_MPEG2 0xc8
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#define HHI_GCLK2_OTHER 0xd0
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#define HHI_GCLK2_AO 0xd4
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#define HHI_PCIE_PLL_CNTL 0xd8
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#define HHI_PCIE_PLL_CNTL1 0xdC
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#define HHI_PCIE_PLL_CNTL2 0xe0
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#define HHI_PCIE_PLL_CNTL3 0xe4
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#define HHI_PCIE_PLL_CNTL4 0xe8
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#define HHI_PCIE_PLL_CNTL5 0xec
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#define HHI_PCIE_PLL_CNTL6 0xf0
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#define HHI_PCIE_PLL_STS 0xf4
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#define HHI_MEM_PD_REG0 0x100
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#define HHI_VPU_MEM_PD_REG0 0x104
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#define HHI_VIID_CLK_DIV 0x128
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#define HHI_VIID_CLK_CNTL 0x12c
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#define HHI_GCLK_MPEG0 0x140
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#define HHI_GCLK_MPEG1 0x144
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#define HHI_GCLK_MPEG2 0x148
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#define HHI_GCLK_OTHER 0x150
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#define HHI_GCLK_AO 0x154
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c
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#define HHI_SYS_CPU_RESET_CNTL 0x160
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#define HHI_VID_CLK_DIV 0x164
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#define HHI_SPICC_HCLK_CNTL 0x168
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#define HHI_MPEG_CLK_CNTL 0x174
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#define HHI_VID_CLK_CNTL 0x17c
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#define HHI_TS_CLK_CNTL 0x190
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#define HHI_VID_CLK_CNTL2 0x194
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c
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#define HHI_VID_PLL_CLK_DIV 0x1a0
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#define HHI_VPU_CLK_CNTL 0x1bC
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#define HHI_VAPBCLK_CNTL 0x1F4
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#define HHI_GEN_CLK_CNTL 0x228
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#define HHI_VDIN_MEAS_CLK_CNTL 0x250
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#define HHI_NAND_CLK_CNTL 0x25C
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#define HHI_SD_EMMC_CLK_CNTL 0x264
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#define HHI_MPLL_CNTL 0x280
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#define HHI_MPLL_CNTL2 0x284
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#define HHI_MPLL_CNTL3 0x288
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#define HHI_MPLL_CNTL4 0x28C
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#define HHI_MPLL_CNTL5 0x290
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#define HHI_MPLL_CNTL6 0x294
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#define HHI_MPLL_CNTL7 0x298
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#define HHI_MPLL_CNTL8 0x29C
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#define HHI_MPLL_CNTL9 0x2A0
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#define HHI_MPLL_CNTL10 0x2A4
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#define HHI_MPLL3_CNTL0 0x2E0
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#define HHI_MPLL3_CNTL1 0x2E4
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#define HHI_PLL_TOP_MISC 0x2E8
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#define HHI_SYS_PLL_CNTL1 0x2FC
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#define HHI_SYS_PLL_CNTL 0x300
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#define HHI_SYS_PLL_CNTL2 0x304
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#define HHI_SYS_PLL_CNTL3 0x308
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#define HHI_SYS_PLL_CNTL4 0x30c
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#define HHI_SYS_PLL_CNTL5 0x310
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#define HHI_SYS_PLL_STS 0x314
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#define HHI_DPLL_TOP_I 0x318
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#define HHI_DPLL_TOP2_I 0x31C
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/*
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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#define CLKID_MPEG_SEL 8
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#define CLKID_MPEG_DIV 9
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#define CLKID_SD_EMMC_B_CLK0_SEL 61
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#define CLKID_SD_EMMC_B_CLK0_DIV 62
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#define CLKID_SD_EMMC_C_CLK0_SEL 63
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#define CLKID_SD_EMMC_C_CLK0_DIV 64
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#define CLKID_MPLL0_DIV 65
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#define CLKID_MPLL1_DIV 66
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#define CLKID_MPLL2_DIV 67
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#define CLKID_MPLL3_DIV 68
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#define CLKID_MPLL_PREDIV 70
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#define CLKID_FCLK_DIV2_DIV 71
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#define CLKID_FCLK_DIV3_DIV 72
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#define CLKID_FCLK_DIV4_DIV 73
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#define CLKID_FCLK_DIV5_DIV 74
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#define CLKID_FCLK_DIV7_DIV 75
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#define CLKID_PCIE_PLL 76
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#define CLKID_PCIE_MUX 77
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#define CLKID_PCIE_REF 78
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#define CLKID_GEN_CLK_SEL 82
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#define CLKID_GEN_CLK_DIV 83
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#define NR_CLKS 85
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/axg-clkc.h>
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#endif /* __AXG_H */
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