727 lines
14 KiB
ArmAsm
727 lines
14 KiB
ArmAsm
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* This file contains the low-level entry-points into the kernel, that is,
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* exception handlers, debug trap handlers, interrupt handlers and the
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* system call handler.
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*/
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#include <linux/errno.h>
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#include <asm/asm.h>
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#include <asm/hardirq.h>
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#include <asm/irq.h>
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#include <asm/ocd.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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#include <asm/thread_info.h>
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#include <asm/unistd.h>
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#ifdef CONFIG_PREEMPT
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# define preempt_stop mask_interrupts
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#else
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# define preempt_stop
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# define fault_resume_kernel fault_restore_all
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#endif
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#define __MASK(x) ((1 << (x)) - 1)
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#define IRQ_MASK ((__MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) | \
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(__MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT))
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.section .ex.text,"ax",@progbits
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.align 2
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exception_vectors:
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bral handle_critical
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.align 2
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bral handle_critical
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.align 2
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bral do_bus_error_write
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.align 2
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bral do_bus_error_read
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.align 2
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bral do_nmi_ll
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.align 2
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bral handle_address_fault
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.align 2
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bral handle_protection_fault
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.align 2
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bral handle_debug
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.align 2
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bral do_illegal_opcode_ll
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.align 2
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bral do_illegal_opcode_ll
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.align 2
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bral do_illegal_opcode_ll
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.align 2
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bral do_fpe_ll
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.align 2
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bral do_illegal_opcode_ll
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.align 2
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bral handle_address_fault
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.align 2
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bral handle_address_fault
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.align 2
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bral handle_protection_fault
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.align 2
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bral handle_protection_fault
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.align 2
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bral do_dtlb_modified
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/*
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* r0 : PGD/PT/PTE
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* r1 : Offending address
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* r2 : Scratch register
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* r3 : Cause (5, 12 or 13)
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*/
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#define tlbmiss_save pushm r0-r3
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#define tlbmiss_restore popm r0-r3
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.section .tlbx.ex.text,"ax",@progbits
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.global itlb_miss
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itlb_miss:
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tlbmiss_save
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rjmp tlb_miss_common
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.section .tlbr.ex.text,"ax",@progbits
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dtlb_miss_read:
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tlbmiss_save
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rjmp tlb_miss_common
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.section .tlbw.ex.text,"ax",@progbits
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dtlb_miss_write:
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tlbmiss_save
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.global tlb_miss_common
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tlb_miss_common:
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mfsr r0, SYSREG_TLBEAR
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mfsr r1, SYSREG_PTBR
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/* Is it the vmalloc space? */
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bld r0, 31
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brcs handle_vmalloc_miss
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/* First level lookup */
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pgtbl_lookup:
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lsr r2, r0, PGDIR_SHIFT
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ld.w r3, r1[r2 << 2]
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bfextu r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
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bld r3, _PAGE_BIT_PRESENT
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brcc page_table_not_present
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/* Translate to virtual address in P1. */
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andl r3, 0xf000
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sbr r3, 31
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/* Second level lookup */
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ld.w r2, r3[r1 << 2]
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mfsr r0, SYSREG_TLBARLO
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bld r2, _PAGE_BIT_PRESENT
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brcc page_not_present
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/* Mark the page as accessed */
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sbr r2, _PAGE_BIT_ACCESSED
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st.w r3[r1 << 2], r2
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/* Drop software flags */
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andl r2, _PAGE_FLAGS_HARDWARE_MASK & 0xffff
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mtsr SYSREG_TLBELO, r2
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/* Figure out which entry we want to replace */
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mfsr r1, SYSREG_MMUCR
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clz r2, r0
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brcc 1f
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mov r3, -1 /* All entries have been accessed, */
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mov r2, 0 /* so start at 0 */
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mtsr SYSREG_TLBARLO, r3 /* and reset TLBAR */
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1: bfins r1, r2, SYSREG_DRP_OFFSET, SYSREG_DRP_SIZE
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mtsr SYSREG_MMUCR, r1
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tlbw
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tlbmiss_restore
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rete
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handle_vmalloc_miss:
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/* Simply do the lookup in init's page table */
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mov r1, lo(swapper_pg_dir)
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orh r1, hi(swapper_pg_dir)
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rjmp pgtbl_lookup
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/* --- System Call --- */
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.section .scall.text,"ax",@progbits
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system_call:
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pushm r12 /* r12_orig */
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stmts --sp, r0-lr
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zero_fp
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mfsr r0, SYSREG_RAR_SUP
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mfsr r1, SYSREG_RSR_SUP
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stm --sp, r0-r1
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/* check for syscall tracing */
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get_thread_info r0
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ld.w r1, r0[TI_flags]
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bld r1, TIF_SYSCALL_TRACE
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brcs syscall_trace_enter
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syscall_trace_cont:
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cp.w r8, NR_syscalls
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brhs syscall_badsys
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lddpc lr, syscall_table_addr
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ld.w lr, lr[r8 << 2]
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mov r8, r5 /* 5th argument (6th is pushed by stub) */
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icall lr
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.global syscall_return
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syscall_return:
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get_thread_info r0
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mask_interrupts /* make sure we don't miss an interrupt
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setting need_resched or sigpending
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between sampling and the rets */
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/* Store the return value so that the correct value is loaded below */
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stdsp sp[REG_R12], r12
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ld.w r1, r0[TI_flags]
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andl r1, _TIF_ALLWORK_MASK, COH
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brne syscall_exit_work
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syscall_exit_cont:
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popm r8-r9
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mtsr SYSREG_RAR_SUP, r8
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mtsr SYSREG_RSR_SUP, r9
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ldmts sp++, r0-lr
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sub sp, -4 /* r12_orig */
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rets
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.align 2
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syscall_table_addr:
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.long sys_call_table
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syscall_badsys:
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mov r12, -ENOSYS
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rjmp syscall_return
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.global ret_from_fork
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ret_from_fork:
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rcall schedule_tail
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/* check for syscall tracing */
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get_thread_info r0
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ld.w r1, r0[TI_flags]
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andl r1, _TIF_ALLWORK_MASK, COH
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brne syscall_exit_work
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rjmp syscall_exit_cont
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syscall_trace_enter:
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pushm r8-r12
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rcall syscall_trace
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popm r8-r12
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rjmp syscall_trace_cont
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syscall_exit_work:
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bld r1, TIF_SYSCALL_TRACE
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brcc 1f
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unmask_interrupts
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rcall syscall_trace
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mask_interrupts
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ld.w r1, r0[TI_flags]
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1: bld r1, TIF_NEED_RESCHED
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brcc 2f
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unmask_interrupts
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rcall schedule
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mask_interrupts
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ld.w r1, r0[TI_flags]
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rjmp 1b
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2: mov r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
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tst r1, r2
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breq 3f
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unmask_interrupts
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mov r12, sp
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mov r11, r0
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rcall do_notify_resume
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mask_interrupts
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ld.w r1, r0[TI_flags]
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rjmp 1b
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3: bld r1, TIF_BREAKPOINT
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brcc syscall_exit_cont
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mfsr r3, SYSREG_TLBEHI
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lddsp r2, sp[REG_PC]
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andl r3, 0xff, COH
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lsl r3, 1
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sbr r3, 30
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sbr r3, 0
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mtdr DBGREG_BWA2A, r2
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mtdr DBGREG_BWC2A, r3
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rjmp syscall_exit_cont
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/* The slow path of the TLB miss handler */
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page_table_not_present:
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page_not_present:
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tlbmiss_restore
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_page_fault
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rjmp ret_from_exception
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/* This function expects to find offending PC in SYSREG_RAR_EX */
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save_full_context_ex:
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mfsr r8, SYSREG_RSR_EX
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mov r12, r8
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andh r8, (MODE_MASK >> 16), COH
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mfsr r11, SYSREG_RAR_EX
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brne 2f
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1: pushm r11, r12 /* PC and SR */
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unmask_exceptions
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ret r12
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2: sub r10, sp, -(FRAME_SIZE_FULL - REG_LR)
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stdsp sp[4], r10 /* replace saved SP */
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rjmp 1b
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/* Low-level exception handlers */
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handle_critical:
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pushm r12
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pushm r0-r12
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_critical_exception
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/* We should never get here... */
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bad_return:
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sub r12, pc, (. - 1f)
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bral panic
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.align 2
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1: .asciz "Return from critical exception!"
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.align 1
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do_bus_error_write:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mov r11, 1
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rjmp 1f
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do_bus_error_read:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mov r11, 0
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1: mfsr r12, SYSREG_BEAR
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mov r10, sp
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rcall do_bus_error
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rjmp ret_from_exception
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.align 1
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do_nmi_ll:
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sub sp, 4
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stmts --sp, r0-lr
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mfsr r9, SYSREG_RSR_NMI
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mfsr r8, SYSREG_RAR_NMI
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bfextu r0, r9, MODE_SHIFT, 3
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brne 2f
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1: pushm r8, r9 /* PC and SR */
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_nmi
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popm r8-r9
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mtsr SYSREG_RAR_NMI, r8
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tst r0, r0
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mtsr SYSREG_RSR_NMI, r9
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brne 3f
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ldmts sp++, r0-lr
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sub sp, -4 /* skip r12_orig */
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rete
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2: sub r10, sp, -(FRAME_SIZE_FULL - REG_LR)
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stdsp sp[4], r10 /* replace saved SP */
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rjmp 1b
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3: popm lr
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sub sp, -4 /* skip sp */
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popm r0-r12
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sub sp, -4 /* skip r12_orig */
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rete
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handle_address_fault:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_address_exception
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rjmp ret_from_exception
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handle_protection_fault:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_page_fault
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rjmp ret_from_exception
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.align 1
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do_illegal_opcode_ll:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_illegal_opcode
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rjmp ret_from_exception
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do_dtlb_modified:
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pushm r0-r3
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mfsr r1, SYSREG_TLBEAR
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mfsr r0, SYSREG_PTBR
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lsr r2, r1, PGDIR_SHIFT
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ld.w r0, r0[r2 << 2]
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lsl r1, (32 - PGDIR_SHIFT)
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lsr r1, (32 - PGDIR_SHIFT) + PAGE_SHIFT
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/* Translate to virtual address in P1 */
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andl r0, 0xf000
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sbr r0, 31
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add r2, r0, r1 << 2
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ld.w r3, r2[0]
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sbr r3, _PAGE_BIT_DIRTY
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mov r0, r3
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st.w r2[0], r3
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/* The page table is up-to-date. Update the TLB entry as well */
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andl r0, lo(_PAGE_FLAGS_HARDWARE_MASK)
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mtsr SYSREG_TLBELO, r0
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/* MMUCR[DRP] is updated automatically, so let's go... */
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tlbw
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popm r0-r3
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rete
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do_fpe_ll:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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unmask_interrupts
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mov r12, 26
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mov r11, sp
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rcall do_fpe
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rjmp ret_from_exception
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ret_from_exception:
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mask_interrupts
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lddsp r4, sp[REG_SR]
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andh r4, (MODE_MASK >> 16), COH
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brne fault_resume_kernel
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get_thread_info r0
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ld.w r1, r0[TI_flags]
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andl r1, _TIF_WORK_MASK, COH
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brne fault_exit_work
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fault_resume_user:
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popm r8-r9
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mask_exceptions
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mtsr SYSREG_RAR_EX, r8
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mtsr SYSREG_RSR_EX, r9
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ldmts sp++, r0-lr
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sub sp, -4
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rete
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fault_resume_kernel:
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#ifdef CONFIG_PREEMPT
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get_thread_info r0
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ld.w r2, r0[TI_preempt_count]
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cp.w r2, 0
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brne 1f
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ld.w r1, r0[TI_flags]
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bld r1, TIF_NEED_RESCHED
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brcc 1f
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lddsp r4, sp[REG_SR]
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bld r4, SYSREG_GM_OFFSET
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brcs 1f
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rcall preempt_schedule_irq
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1:
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#endif
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popm r8-r9
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mask_exceptions
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mfsr r1, SYSREG_SR
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mtsr SYSREG_RAR_EX, r8
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mtsr SYSREG_RSR_EX, r9
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popm lr
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sub sp, -4 /* ignore SP */
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popm r0-r12
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sub sp, -4 /* ignore r12_orig */
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rete
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irq_exit_work:
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/* Switch to exception mode so that we can share the same code. */
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mfsr r8, SYSREG_SR
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cbr r8, SYSREG_M0_OFFSET
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orh r8, hi(SYSREG_BIT(M1) | SYSREG_BIT(M2))
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mtsr SYSREG_SR, r8
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sub pc, -2
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get_thread_info r0
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ld.w r1, r0[TI_flags]
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fault_exit_work:
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bld r1, TIF_NEED_RESCHED
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brcc 1f
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unmask_interrupts
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rcall schedule
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mask_interrupts
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ld.w r1, r0[TI_flags]
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rjmp fault_exit_work
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1: mov r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
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tst r1, r2
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breq 2f
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unmask_interrupts
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mov r12, sp
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mov r11, r0
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rcall do_notify_resume
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mask_interrupts
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ld.w r1, r0[TI_flags]
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rjmp fault_exit_work
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2: bld r1, TIF_BREAKPOINT
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brcc fault_resume_user
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mfsr r3, SYSREG_TLBEHI
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lddsp r2, sp[REG_PC]
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andl r3, 0xff, COH
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lsl r3, 1
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sbr r3, 30
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sbr r3, 0
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mtdr DBGREG_BWA2A, r2
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mtdr DBGREG_BWC2A, r3
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rjmp fault_resume_user
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/* If we get a debug trap from privileged context we end up here */
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handle_debug_priv:
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/* Fix up LR and SP in regs. r11 contains the mode we came from */
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mfsr r8, SYSREG_SR
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mov r9, r8
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andh r8, hi(~MODE_MASK)
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or r8, r11
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mtsr SYSREG_SR, r8
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sub pc, -2
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stdsp sp[REG_LR], lr
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mtsr SYSREG_SR, r9
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sub pc, -2
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sub r10, sp, -FRAME_SIZE_FULL
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stdsp sp[REG_SP], r10
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mov r12, sp
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rcall do_debug_priv
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/* Now, put everything back */
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ssrf SR_EM_BIT
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popm r10, r11
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mtsr SYSREG_RAR_DBG, r10
|
|
mtsr SYSREG_RSR_DBG, r11
|
|
mfsr r8, SYSREG_SR
|
|
mov r9, r8
|
|
andh r8, hi(~MODE_MASK)
|
|
andh r11, hi(MODE_MASK)
|
|
or r8, r11
|
|
mtsr SYSREG_SR, r8
|
|
sub pc, -2
|
|
popm lr
|
|
mtsr SYSREG_SR, r9
|
|
sub pc, -2
|
|
sub sp, -4 /* skip SP */
|
|
popm r0-r12
|
|
sub sp, -4
|
|
retd
|
|
|
|
/*
|
|
* At this point, everything is masked, that is, interrupts,
|
|
* exceptions and debugging traps. We might get called from
|
|
* interrupt or exception context in some rare cases, but this
|
|
* will be taken care of by do_debug(), so we're not going to
|
|
* do a 100% correct context save here.
|
|
*/
|
|
handle_debug:
|
|
sub sp, 4 /* r12_orig */
|
|
stmts --sp, r0-lr
|
|
mfsr r10, SYSREG_RAR_DBG
|
|
mfsr r11, SYSREG_RSR_DBG
|
|
unmask_exceptions
|
|
pushm r10,r11
|
|
andh r11, (MODE_MASK >> 16), COH
|
|
brne handle_debug_priv
|
|
|
|
mov r12, sp
|
|
rcall do_debug
|
|
|
|
lddsp r10, sp[REG_SR]
|
|
andh r10, (MODE_MASK >> 16), COH
|
|
breq debug_resume_user
|
|
|
|
debug_restore_all:
|
|
popm r10,r11
|
|
mask_exceptions
|
|
mtsr SYSREG_RSR_DBG, r11
|
|
mtsr SYSREG_RAR_DBG, r10
|
|
ldmts sp++, r0-lr
|
|
sub sp, -4
|
|
retd
|
|
|
|
debug_resume_user:
|
|
get_thread_info r0
|
|
mask_interrupts
|
|
|
|
ld.w r1, r0[TI_flags]
|
|
andl r1, _TIF_DBGWORK_MASK, COH
|
|
breq debug_restore_all
|
|
|
|
1: bld r1, TIF_NEED_RESCHED
|
|
brcc 2f
|
|
unmask_interrupts
|
|
rcall schedule
|
|
mask_interrupts
|
|
ld.w r1, r0[TI_flags]
|
|
rjmp 1b
|
|
|
|
2: mov r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
|
|
tst r1, r2
|
|
breq 3f
|
|
unmask_interrupts
|
|
mov r12, sp
|
|
mov r11, r0
|
|
rcall do_notify_resume
|
|
mask_interrupts
|
|
ld.w r1, r0[TI_flags]
|
|
rjmp 1b
|
|
|
|
3: bld r1, TIF_SINGLE_STEP
|
|
brcc debug_restore_all
|
|
mfdr r2, DBGREG_DC
|
|
sbr r2, DC_SS_BIT
|
|
mtdr DBGREG_DC, r2
|
|
rjmp debug_restore_all
|
|
|
|
.set rsr_int0, SYSREG_RSR_INT0
|
|
.set rsr_int1, SYSREG_RSR_INT1
|
|
.set rsr_int2, SYSREG_RSR_INT2
|
|
.set rsr_int3, SYSREG_RSR_INT3
|
|
.set rar_int0, SYSREG_RAR_INT0
|
|
.set rar_int1, SYSREG_RAR_INT1
|
|
.set rar_int2, SYSREG_RAR_INT2
|
|
.set rar_int3, SYSREG_RAR_INT3
|
|
|
|
.macro IRQ_LEVEL level
|
|
.type irq_level\level, @function
|
|
irq_level\level:
|
|
sub sp, 4 /* r12_orig */
|
|
stmts --sp,r0-lr
|
|
mfsr r8, rar_int\level
|
|
mfsr r9, rsr_int\level
|
|
pushm r8-r9
|
|
|
|
mov r11, sp
|
|
mov r12, \level
|
|
|
|
rcall do_IRQ
|
|
|
|
lddsp r4, sp[REG_SR]
|
|
bfextu r4, r4, SYSREG_M0_OFFSET, 3
|
|
cp.w r4, MODE_SUPERVISOR >> SYSREG_M0_OFFSET
|
|
breq 2f
|
|
cp.w r4, MODE_USER >> SYSREG_M0_OFFSET
|
|
#ifdef CONFIG_PREEMPT
|
|
brne 3f
|
|
#else
|
|
brne 1f
|
|
#endif
|
|
|
|
get_thread_info r0
|
|
ld.w r1, r0[TI_flags]
|
|
andl r1, _TIF_WORK_MASK, COH
|
|
brne irq_exit_work
|
|
|
|
1: popm r8-r9
|
|
mtsr rar_int\level, r8
|
|
mtsr rsr_int\level, r9
|
|
ldmts sp++,r0-lr
|
|
sub sp, -4 /* ignore r12_orig */
|
|
rete
|
|
|
|
2: get_thread_info r0
|
|
ld.w r1, r0[TI_flags]
|
|
bld r1, TIF_CPU_GOING_TO_SLEEP
|
|
#ifdef CONFIG_PREEMPT
|
|
brcc 3f
|
|
#else
|
|
brcc 1b
|
|
#endif
|
|
sub r1, pc, . - cpu_idle_skip_sleep
|
|
stdsp sp[REG_PC], r1
|
|
#ifdef CONFIG_PREEMPT
|
|
3: get_thread_info r0
|
|
ld.w r2, r0[TI_preempt_count]
|
|
cp.w r2, 0
|
|
brne 1b
|
|
ld.w r1, r0[TI_flags]
|
|
bld r1, TIF_NEED_RESCHED
|
|
brcc 1b
|
|
lddsp r4, sp[REG_SR]
|
|
bld r4, SYSREG_GM_OFFSET
|
|
brcs 1b
|
|
rcall preempt_schedule_irq
|
|
#endif
|
|
rjmp 1b
|
|
.endm
|
|
|
|
.section .irq.text,"ax",@progbits
|
|
|
|
.global cpu_idle_sleep
|
|
cpu_idle_sleep:
|
|
mask_interrupts
|
|
get_thread_info r8
|
|
ld.w r9, r8[TI_flags]
|
|
bld r9, TIF_NEED_RESCHED
|
|
brcs cpu_idle_enable_int_and_exit
|
|
sbr r9, TIF_CPU_GOING_TO_SLEEP
|
|
st.w r8[TI_flags], r9
|
|
unmask_interrupts
|
|
sleep 0
|
|
cpu_idle_skip_sleep:
|
|
mask_interrupts
|
|
ld.w r9, r8[TI_flags]
|
|
cbr r9, TIF_CPU_GOING_TO_SLEEP
|
|
st.w r8[TI_flags], r9
|
|
cpu_idle_enable_int_and_exit:
|
|
unmask_interrupts
|
|
retal r12
|
|
|
|
.global irq_level0
|
|
.global irq_level1
|
|
.global irq_level2
|
|
.global irq_level3
|
|
IRQ_LEVEL 0
|
|
IRQ_LEVEL 1
|
|
IRQ_LEVEL 2
|
|
IRQ_LEVEL 3
|