214 lines
6.5 KiB
C
214 lines
6.5 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#ifndef __AMDGPU_VM_H__
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#define __AMDGPU_VM_H__
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#include <linux/rbtree.h>
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#include "gpu_scheduler.h"
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#include "amdgpu_sync.h"
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#include "amdgpu_ring.h"
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struct amdgpu_bo_va;
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struct amdgpu_job;
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struct amdgpu_bo_list_entry;
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/*
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* GPUVM handling
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*/
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/* maximum number of VMIDs */
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#define AMDGPU_NUM_VM 16
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/* Maximum number of PTEs the hardware can write with one command */
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#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
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/* number of entries in page table */
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#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
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/* PTBs (Page Table Blocks) need to be aligned to 32K */
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#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
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/* LOG2 number of continuous pages for the fragment field */
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#define AMDGPU_LOG2_PAGES_PER_FRAG 4
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#define AMDGPU_PTE_VALID (1ULL << 0)
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#define AMDGPU_PTE_SYSTEM (1ULL << 1)
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#define AMDGPU_PTE_SNOOPED (1ULL << 2)
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/* VI only */
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#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
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#define AMDGPU_PTE_READABLE (1ULL << 5)
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#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
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#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
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#define AMDGPU_PTE_PRT (1ULL << 63)
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/* How to programm VM fault handling */
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#define AMDGPU_VM_FAULT_STOP_NEVER 0
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#define AMDGPU_VM_FAULT_STOP_FIRST 1
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#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
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struct amdgpu_vm_pt {
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struct amdgpu_bo *bo;
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uint64_t addr;
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};
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struct amdgpu_vm {
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/* tree of virtual addresses mapped */
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struct rb_root va;
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/* protecting invalidated */
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spinlock_t status_lock;
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/* BOs moved, but not yet updated in the PT */
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struct list_head invalidated;
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/* BOs cleared in the PT because of a move */
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struct list_head cleared;
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/* BO mappings freed, but not yet updated in the PT */
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struct list_head freed;
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/* contains the page directory */
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struct amdgpu_bo *page_directory;
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unsigned max_pde_used;
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struct dma_fence *page_directory_fence;
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uint64_t last_eviction_counter;
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/* array of page tables, one for each page directory entry */
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struct amdgpu_vm_pt *page_tables;
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/* for id and flush management per ring */
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struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
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/* protecting freed */
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spinlock_t freed_lock;
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/* Scheduler entity for page table updates */
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struct amd_sched_entity entity;
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/* client id */
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u64 client_id;
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/* each VM will map on CSA */
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struct amdgpu_bo_va *csa_bo_va;
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};
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struct amdgpu_vm_id {
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struct list_head list;
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struct dma_fence *first;
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struct amdgpu_sync active;
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struct dma_fence *last_flush;
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atomic64_t owner;
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uint64_t pd_gpu_addr;
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/* last flushed PD/PT update */
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struct dma_fence *flushed_updates;
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uint32_t current_gpu_reset_count;
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uint32_t gds_base;
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uint32_t gds_size;
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uint32_t gws_base;
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uint32_t gws_size;
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uint32_t oa_base;
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uint32_t oa_size;
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};
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struct amdgpu_vm_manager {
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/* Handling of VMIDs */
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struct mutex lock;
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unsigned num_ids;
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struct list_head ids_lru;
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struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
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/* Handling of VM fences */
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u64 fence_context;
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unsigned seqno[AMDGPU_MAX_RINGS];
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uint32_t max_pfn;
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/* vram base address for page table entry */
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u64 vram_base_offset;
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/* is vm enabled? */
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bool enabled;
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/* vm pte handling */
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const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
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struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
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unsigned vm_pte_num_rings;
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atomic_t vm_pte_next_ring;
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/* client id counter */
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atomic64_t client_counter;
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/* partial resident texture handling */
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spinlock_t prt_lock;
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atomic_t num_prt_users;
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};
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void amdgpu_vm_manager_init(struct amdgpu_device *adev);
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void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
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int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
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void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
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void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
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struct list_head *validated,
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struct amdgpu_bo_list_entry *entry);
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int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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int (*callback)(void *p, struct amdgpu_bo *bo),
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void *param);
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void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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struct amdgpu_sync *sync, struct dma_fence *fence,
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struct amdgpu_job *job);
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int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
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void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
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int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct amdgpu_sync *sync);
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int amdgpu_vm_bo_update(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va,
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bool clear);
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void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
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struct amdgpu_bo *bo);
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struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
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struct amdgpu_bo *bo);
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struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_bo *bo);
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int amdgpu_vm_bo_map(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va,
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uint64_t addr, uint64_t offset,
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uint64_t size, uint64_t flags);
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int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va,
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uint64_t addr);
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void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va);
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#endif
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