104 lines
2.6 KiB
ArmAsm
104 lines
2.6 KiB
ArmAsm
/*
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* sh7372 lowlevel sleep code for "Core Standby Mode"
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*
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* Copyright (C) 2011 Magnus Damm
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*
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* In "Core Standby Mode" the ARM core is off, but L2 cache is still on
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*
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* Based on mach-omap2/sleep34xx.S
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*
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* (C) Copyright 2007 Texas Instruments
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* Karthik Dasu <karthik-dp@ti.com>
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*
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* (C) Copyright 2004 Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/memory.h>
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#include <asm/assembler.h>
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#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
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.align 12
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.text
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.global sh7372_resume_core_standby_sysc
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sh7372_resume_core_standby_sysc:
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ldr pc, 1f
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.align 2
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.globl sh7372_cpu_resume
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sh7372_cpu_resume:
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1: .space 4
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#define SPDCR 0xe6180008
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/* A3SM & A4S power down */
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.global sh7372_do_idle_sysc
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sh7372_do_idle_sysc:
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mov r8, r0 /* sleep mode passed in r0 */
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/*
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* Clear the SCTLR.C bit to prevent further data cache
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* allocation. Clearing SCTLR.C would make all the data accesses
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* strongly ordered and would not hit the cache.
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 2) @ Disable the C bit
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mcr p15, 0, r0, c1, c0, 0
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isb
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/*
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* Clean and invalidate data cache again.
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*/
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ldr r1, kernel_flush
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blx r1
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/* disable L2 cache in the aux control register */
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mrc p15, 0, r10, c1, c0, 1
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bic r10, r10, #2
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mcr p15, 0, r10, c1, c0, 1
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isb
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/*
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* The kernel doesn't interwork: v7_flush_dcache_all in particluar will
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* always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
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* This sequence switches back to ARM. Note that .align may insert a
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* nop: bx pc needs to be word-aligned in order to work.
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*/
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THUMB( .thumb )
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THUMB( .align )
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THUMB( bx pc )
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THUMB( nop )
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.arm
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/* Data memory barrier and Data sync barrier */
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dsb
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dmb
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/* SYSC power down */
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ldr r0, =SPDCR
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str r8, [r0]
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1:
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b 1b
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.align 2
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kernel_flush:
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.word v7_flush_dcache_all
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#endif
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