217 lines
5.5 KiB
C
217 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <uapi/linux/idxd.h>
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#include "idxd.h"
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#include "registers.h"
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static struct idxd_desc *__get_desc(struct idxd_wq *wq, int idx, int cpu)
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{
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struct idxd_desc *desc;
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struct idxd_device *idxd = wq->idxd;
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desc = wq->descs[idx];
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memset(desc->hw, 0, sizeof(struct dsa_hw_desc));
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memset(desc->completion, 0, idxd->data->compl_size);
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desc->cpu = cpu;
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if (device_pasid_enabled(idxd))
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desc->hw->pasid = idxd->pasid;
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return desc;
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}
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struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype)
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{
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int cpu, idx;
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struct idxd_device *idxd = wq->idxd;
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DEFINE_SBQ_WAIT(wait);
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struct sbq_wait_state *ws;
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struct sbitmap_queue *sbq;
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if (idxd->state != IDXD_DEV_ENABLED)
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return ERR_PTR(-EIO);
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sbq = &wq->sbq;
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idx = sbitmap_queue_get(sbq, &cpu);
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if (idx < 0) {
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if (optype == IDXD_OP_NONBLOCK)
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return ERR_PTR(-EAGAIN);
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} else {
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return __get_desc(wq, idx, cpu);
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}
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ws = &sbq->ws[0];
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for (;;) {
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sbitmap_prepare_to_wait(sbq, ws, &wait, TASK_INTERRUPTIBLE);
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if (signal_pending_state(TASK_INTERRUPTIBLE, current))
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break;
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idx = sbitmap_queue_get(sbq, &cpu);
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if (idx >= 0)
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break;
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schedule();
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}
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sbitmap_finish_wait(sbq, ws, &wait);
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if (idx < 0)
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return ERR_PTR(-EAGAIN);
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return __get_desc(wq, idx, cpu);
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}
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void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc)
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{
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int cpu = desc->cpu;
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desc->cpu = -1;
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sbitmap_queue_clear(&wq->sbq, desc->id, cpu);
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}
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static struct idxd_desc *list_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie,
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struct idxd_desc *desc)
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{
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struct idxd_desc *d, *n;
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lockdep_assert_held(&ie->list_lock);
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list_for_each_entry_safe(d, n, &ie->work_list, list) {
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if (d == desc) {
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list_del(&d->list);
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return d;
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}
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}
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/*
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* At this point, the desc needs to be aborted is held by the completion
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* handler where it has taken it off the pending list but has not added to the
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* work list. It will be cleaned up by the interrupt handler when it sees the
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* IDXD_COMP_DESC_ABORT for completion status.
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*/
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return NULL;
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}
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static void llist_abort_desc(struct idxd_wq *wq, struct idxd_irq_entry *ie,
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struct idxd_desc *desc)
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{
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struct idxd_desc *d, *t, *found = NULL;
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struct llist_node *head;
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LIST_HEAD(flist);
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desc->completion->status = IDXD_COMP_DESC_ABORT;
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/*
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* Grab the list lock so it will block the irq thread handler. This allows the
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* abort code to locate the descriptor need to be aborted.
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*/
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spin_lock(&ie->list_lock);
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head = llist_del_all(&ie->pending_llist);
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if (head) {
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llist_for_each_entry_safe(d, t, head, llnode) {
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if (d == desc) {
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found = desc;
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continue;
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}
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if (d->completion->status)
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list_add_tail(&d->list, &flist);
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else
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list_add_tail(&d->list, &ie->work_list);
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}
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}
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if (!found)
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found = list_abort_desc(wq, ie, desc);
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spin_unlock(&ie->list_lock);
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if (found)
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idxd_dma_complete_txd(found, IDXD_COMPLETE_ABORT, false);
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/*
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* completing the descriptor will return desc to allocator and
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* the desc can be acquired by a different process and the
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* desc->list can be modified. Delete desc from list so the
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* list trasversing does not get corrupted by the other process.
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*/
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list_for_each_entry_safe(d, t, &flist, list) {
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list_del_init(&d->list);
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idxd_dma_complete_txd(found, IDXD_COMPLETE_ABORT, true);
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}
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}
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/*
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* ENQCMDS typically fail when the WQ is inactive or busy. On host submission, the driver
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* has better control of number of descriptors being submitted to a shared wq by limiting
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* the number of driver allocated descriptors to the wq size. However, when the swq is
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* exported to a guest kernel, it may be shared with multiple guest kernels. This means
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* the likelihood of getting busy returned on the swq when submitting goes significantly up.
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* Having a tunable retry mechanism allows the driver to keep trying for a bit before giving
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* up. The sysfs knob can be tuned by the system administrator.
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*/
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int idxd_enqcmds(struct idxd_wq *wq, void __iomem *portal, const void *desc)
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{
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int rc, retries = 0;
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do {
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rc = enqcmds(portal, desc);
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if (rc == 0)
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break;
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cpu_relax();
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} while (retries++ < wq->enqcmds_retries);
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return rc;
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}
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int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
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{
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struct idxd_device *idxd = wq->idxd;
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struct idxd_irq_entry *ie = NULL;
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u32 desc_flags = desc->hw->flags;
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void __iomem *portal;
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int rc;
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if (idxd->state != IDXD_DEV_ENABLED)
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return -EIO;
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if (!percpu_ref_tryget_live(&wq->wq_active)) {
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wait_for_completion(&wq->wq_resurrect);
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if (!percpu_ref_tryget_live(&wq->wq_active))
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return -ENXIO;
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}
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portal = idxd_wq_portal_addr(wq);
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/*
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* The wmb() flushes writes to coherent DMA data before
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* possibly triggering a DMA read. The wmb() is necessary
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* even on UP because the recipient is a device.
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*/
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wmb();
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/*
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* Pending the descriptor to the lockless list for the irq_entry
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* that we designated the descriptor to.
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*/
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if (desc_flags & IDXD_OP_FLAG_RCI) {
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ie = &wq->ie;
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desc->hw->int_handle = ie->int_handle;
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llist_add(&desc->llnode, &ie->pending_llist);
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}
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if (wq_dedicated(wq)) {
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iosubmit_cmds512(portal, desc->hw, 1);
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} else {
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rc = idxd_enqcmds(wq, portal, desc->hw);
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if (rc < 0) {
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percpu_ref_put(&wq->wq_active);
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/* abort operation frees the descriptor */
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if (ie)
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llist_abort_desc(wq, ie, desc);
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return rc;
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}
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}
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percpu_ref_put(&wq->wq_active);
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return 0;
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}
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