Ajit Kumar Pandey 1fdaaa13b4 clk: x86: Fix clk_gate_flags for RV_CLK_GATE ... In newer SoC we have to clear bit for disabling 48MHz oscillator clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable and disable of 48MHz clock. Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Reviewed-by: Mario Limonciello <Mario.Limonciello@amd.com> Link: https://lore.kernel.org/r/20211212180527.1641362-6-AjitKumar.Pandey@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2022-01-06 17:57:53 -08:00
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Kconfig	clk: intel: Add CGU clock driver for a new SoC	2020-05-26 19:58:52 -07:00
Makefile	clk: x86: Rename clk-lpt to more specific clk-lpss-atom	2021-07-27 14:03:47 -07:00
clk-cgu-pll.c	clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()	2020-07-24 01:55:18 -07:00
clk-cgu.c	clk: intel: Avoid unnecessary memset by improving code	2020-07-24 01:58:15 -07:00
clk-cgu.h	clk: intel: Add CGU clock driver for a new SoC	2020-05-26 19:58:52 -07:00
clk-fch.c	clk: x86: Fix clk_gate_flags for RV_CLK_GATE	2022-01-06 17:57:53 -08:00
clk-lgm.c	clk: intel: Add CGU clock driver for a new SoC	2020-05-26 19:58:52 -07:00
clk-lpss-atom.c	clk: x86: Rename clk-lpt to more specific clk-lpss-atom	2021-07-27 14:03:47 -07:00
clk-pmc-atom.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00