Sergio Paracuellos c16edf5ff8 clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates ... 'clk_init_data' for gates is setting up 'CLK_IS_CRITICAL' flag for all of them. This was being doing because some drivers of this SoC might not be ready to use the clock and we don't wanted the kernel to disable them since default behaviour without clock driver was to set all gate bits to enabled state. After a bit more testing and checking driver code it is safe to remove this flag and just let the kernel to disable those gates that are not in use. No regressions seems to appear. Fixes: 48df7a26f4 ("clk: ralink: add clock driver for mt7621 SoC") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210727055537.11785-1-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2021-08-28 22:24:06 -07:00
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clk-mt7621.c	clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates	2021-08-28 22:24:06 -07:00