93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#define MT8195_PLL_FMAX (3800UL * MHZ)
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#define MT8195_PLL_FMIN (1500UL * MHZ)
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#define MT8195_INTEGER_BITS (8)
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#define MT8195_PCW_BITS (22)
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#define MT8195_POSDIV_SHIFT (24)
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#define MT8195_PLL_EN_BIT (0)
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#define MT8195_PCW_SHIFT (0)
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/*
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* The "en_reg" and "pcw_chg_reg" fields are standard offset register compared
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* with "reg" field, so set zero to imply it.
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* No tuner control in apu pll, so set "tuner_XXX" as zero to imply it.
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* No rst or post divider enable in apu pll, so set "rst_bar_mask" and "en_mask"
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* as zero to imply it.
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*/
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#define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = 0, \
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.flags = 0, \
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.rst_bar_mask = 0, \
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.fmax = MT8195_PLL_FMAX, \
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.fmin = MT8195_PLL_FMIN, \
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.pcwbits = MT8195_PCW_BITS, \
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.pcwibits = MT8195_INTEGER_BITS, \
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.pd_reg = _pd_reg, \
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.pd_shift = MT8195_POSDIV_SHIFT, \
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.tuner_reg = 0, \
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.tuner_en_reg = 0, \
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.tuner_en_bit = 0, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = MT8195_PCW_SHIFT, \
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.pcw_chg_reg = 0, \
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.en_reg = 0, \
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.pll_en_bit = MT8195_PLL_EN_BIT, \
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}
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static const struct mtk_pll_data apusys_plls[] = {
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PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0x00c, 0x00c),
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PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0x01c, 0x01c),
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PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0x02c, 0x02c),
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PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x03c),
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};
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static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_APUSYS_PLL_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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goto free_apusys_pll_data;
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return r;
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free_apusys_pll_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = {
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{ .compatible = "mediatek,mt8195-apusys_pll", },
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{}
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};
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static struct platform_driver clk_mt8195_apusys_pll_drv = {
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.probe = clk_mt8195_apusys_pll_probe,
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.driver = {
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.name = "clk-mt8195-apusys_pll",
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.of_match_table = of_match_clk_mt8195_apusys_pll,
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},
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};
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builtin_platform_driver(clk_mt8195_apusys_pll_drv);
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