587 lines
15 KiB
C
587 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Analog Devices ADAU7118 8 channel PDM-to-I2S/TDM Converter driver
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//
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// Copyright 2019 Analog Devices Inc.
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "adau7118.h"
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#define ADAU7118_DEC_RATIO_MASK GENMASK(1, 0)
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#define ADAU7118_DEC_RATIO(x) FIELD_PREP(ADAU7118_DEC_RATIO_MASK, x)
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#define ADAU7118_CLK_MAP_MASK GENMASK(7, 4)
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#define ADAU7118_SLOT_WIDTH_MASK GENMASK(5, 4)
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#define ADAU7118_SLOT_WIDTH(x) FIELD_PREP(ADAU7118_SLOT_WIDTH_MASK, x)
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#define ADAU7118_TRISTATE_MASK BIT(6)
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#define ADAU7118_TRISTATE(x) FIELD_PREP(ADAU7118_TRISTATE_MASK, x)
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#define ADAU7118_DATA_FMT_MASK GENMASK(3, 1)
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#define ADAU7118_DATA_FMT(x) FIELD_PREP(ADAU7118_DATA_FMT_MASK, x)
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#define ADAU7118_SAI_MODE_MASK BIT(0)
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#define ADAU7118_SAI_MODE(x) FIELD_PREP(ADAU7118_SAI_MODE_MASK, x)
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#define ADAU7118_LRCLK_BCLK_POL_MASK GENMASK(1, 0)
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#define ADAU7118_LRCLK_BCLK_POL(x) \
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FIELD_PREP(ADAU7118_LRCLK_BCLK_POL_MASK, x)
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#define ADAU7118_SPT_SLOT_MASK GENMASK(7, 4)
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#define ADAU7118_SPT_SLOT(x) FIELD_PREP(ADAU7118_SPT_SLOT_MASK, x)
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#define ADAU7118_FULL_SOFT_R_MASK BIT(1)
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#define ADAU7118_FULL_SOFT_R(x) FIELD_PREP(ADAU7118_FULL_SOFT_R_MASK, x)
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struct adau7118_data {
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struct regmap *map;
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struct device *dev;
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struct regulator *iovdd;
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struct regulator *dvdd;
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u32 slot_width;
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u32 slots;
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bool hw_mode;
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bool right_j;
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};
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/* Input Enable */
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static const struct snd_kcontrol_new adau7118_dapm_pdm_control[4] = {
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SOC_DAPM_SINGLE("Capture Switch", ADAU7118_REG_ENABLES, 0, 1, 0),
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SOC_DAPM_SINGLE("Capture Switch", ADAU7118_REG_ENABLES, 1, 1, 0),
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SOC_DAPM_SINGLE("Capture Switch", ADAU7118_REG_ENABLES, 2, 1, 0),
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SOC_DAPM_SINGLE("Capture Switch", ADAU7118_REG_ENABLES, 3, 1, 0),
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};
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static const struct snd_soc_dapm_widget adau7118_widgets_sw[] = {
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/* Input Enable Switches */
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SND_SOC_DAPM_SWITCH("PDM0", SND_SOC_NOPM, 0, 0,
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&adau7118_dapm_pdm_control[0]),
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SND_SOC_DAPM_SWITCH("PDM1", SND_SOC_NOPM, 0, 0,
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&adau7118_dapm_pdm_control[1]),
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SND_SOC_DAPM_SWITCH("PDM2", SND_SOC_NOPM, 0, 0,
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&adau7118_dapm_pdm_control[2]),
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SND_SOC_DAPM_SWITCH("PDM3", SND_SOC_NOPM, 0, 0,
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&adau7118_dapm_pdm_control[3]),
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/* PDM Clocks */
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SND_SOC_DAPM_SUPPLY("PDM_CLK0", ADAU7118_REG_ENABLES, 4, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("PDM_CLK1", ADAU7118_REG_ENABLES, 5, 0, NULL, 0),
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/* Output channels */
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SND_SOC_DAPM_AIF_OUT("AIF1TX1", "Capture", 0, ADAU7118_REG_SPT_CX(0),
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0, 0),
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SND_SOC_DAPM_AIF_OUT("AIF1TX2", "Capture", 0, ADAU7118_REG_SPT_CX(1),
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0, 0),
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SND_SOC_DAPM_AIF_OUT("AIF1TX3", "Capture", 0, ADAU7118_REG_SPT_CX(2),
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0, 0),
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SND_SOC_DAPM_AIF_OUT("AIF1TX4", "Capture", 0, ADAU7118_REG_SPT_CX(3),
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0, 0),
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SND_SOC_DAPM_AIF_OUT("AIF1TX5", "Capture", 0, ADAU7118_REG_SPT_CX(4),
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0, 0),
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SND_SOC_DAPM_AIF_OUT("AIF1TX6", "Capture", 0, ADAU7118_REG_SPT_CX(5),
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0, 0),
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SND_SOC_DAPM_AIF_OUT("AIF1TX7", "Capture", 0, ADAU7118_REG_SPT_CX(6),
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0, 0),
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SND_SOC_DAPM_AIF_OUT("AIF1TX8", "Capture", 0, ADAU7118_REG_SPT_CX(7),
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0, 0),
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};
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static const struct snd_soc_dapm_route adau7118_routes_sw[] = {
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{ "PDM0", "Capture Switch", "PDM_DAT0" },
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{ "PDM1", "Capture Switch", "PDM_DAT1" },
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{ "PDM2", "Capture Switch", "PDM_DAT2" },
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{ "PDM3", "Capture Switch", "PDM_DAT3" },
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{ "AIF1TX1", NULL, "PDM0" },
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{ "AIF1TX2", NULL, "PDM0" },
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{ "AIF1TX3", NULL, "PDM1" },
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{ "AIF1TX4", NULL, "PDM1" },
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{ "AIF1TX5", NULL, "PDM2" },
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{ "AIF1TX6", NULL, "PDM2" },
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{ "AIF1TX7", NULL, "PDM3" },
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{ "AIF1TX8", NULL, "PDM3" },
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{ "Capture", NULL, "PDM_CLK0" },
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{ "Capture", NULL, "PDM_CLK1" },
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};
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static const struct snd_soc_dapm_widget adau7118_widgets_hw[] = {
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SND_SOC_DAPM_AIF_OUT("AIF1TX", "Capture", 0, SND_SOC_NOPM, 0, 0),
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};
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static const struct snd_soc_dapm_route adau7118_routes_hw[] = {
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{ "AIF1TX", NULL, "PDM_DAT0" },
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{ "AIF1TX", NULL, "PDM_DAT1" },
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{ "AIF1TX", NULL, "PDM_DAT2" },
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{ "AIF1TX", NULL, "PDM_DAT3" },
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};
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static const struct snd_soc_dapm_widget adau7118_widgets[] = {
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SND_SOC_DAPM_INPUT("PDM_DAT0"),
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SND_SOC_DAPM_INPUT("PDM_DAT1"),
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SND_SOC_DAPM_INPUT("PDM_DAT2"),
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SND_SOC_DAPM_INPUT("PDM_DAT3"),
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};
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static int adau7118_set_channel_map(struct snd_soc_dai *dai,
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unsigned int tx_num, unsigned int *tx_slot,
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unsigned int rx_num, unsigned int *rx_slot)
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{
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struct adau7118_data *st =
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snd_soc_component_get_drvdata(dai->component);
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int chan, ret;
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dev_dbg(st->dev, "Set channel map, %d", tx_num);
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for (chan = 0; chan < tx_num; chan++) {
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ret = snd_soc_component_update_bits(dai->component,
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ADAU7118_REG_SPT_CX(chan),
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ADAU7118_SPT_SLOT_MASK,
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ADAU7118_SPT_SLOT(tx_slot[chan]));
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int adau7118_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct adau7118_data *st =
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snd_soc_component_get_drvdata(dai->component);
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int ret = 0;
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u32 regval;
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dev_dbg(st->dev, "Set format, fmt:%d\n", fmt);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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ret = snd_soc_component_update_bits(dai->component,
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ADAU7118_REG_SPT_CTRL1,
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ADAU7118_DATA_FMT_MASK,
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ADAU7118_DATA_FMT(0));
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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ret = snd_soc_component_update_bits(dai->component,
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ADAU7118_REG_SPT_CTRL1,
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ADAU7118_DATA_FMT_MASK,
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ADAU7118_DATA_FMT(1));
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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st->right_j = true;
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break;
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default:
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dev_err(st->dev, "Invalid format %d",
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fmt & SND_SOC_DAIFMT_FORMAT_MASK);
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return -EINVAL;
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}
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if (ret < 0)
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return ret;
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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regval = ADAU7118_LRCLK_BCLK_POL(0);
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break;
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case SND_SOC_DAIFMT_NB_IF:
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regval = ADAU7118_LRCLK_BCLK_POL(2);
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break;
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case SND_SOC_DAIFMT_IB_NF:
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regval = ADAU7118_LRCLK_BCLK_POL(1);
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break;
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case SND_SOC_DAIFMT_IB_IF:
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regval = ADAU7118_LRCLK_BCLK_POL(3);
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break;
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default:
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dev_err(st->dev, "Invalid Inv mask %d",
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fmt & SND_SOC_DAIFMT_INV_MASK);
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return -EINVAL;
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}
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ret = snd_soc_component_update_bits(dai->component,
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ADAU7118_REG_SPT_CTRL2,
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ADAU7118_LRCLK_BCLK_POL_MASK,
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regval);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int adau7118_set_tristate(struct snd_soc_dai *dai, int tristate)
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{
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struct adau7118_data *st =
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snd_soc_component_get_drvdata(dai->component);
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int ret;
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dev_dbg(st->dev, "Set tristate, %d\n", tristate);
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ret = snd_soc_component_update_bits(dai->component,
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ADAU7118_REG_SPT_CTRL1,
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ADAU7118_TRISTATE_MASK,
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ADAU7118_TRISTATE(tristate));
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if (ret < 0)
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return ret;
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return 0;
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}
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static int adau7118_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
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unsigned int rx_mask, int slots,
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int slot_width)
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{
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struct adau7118_data *st =
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snd_soc_component_get_drvdata(dai->component);
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int ret = 0;
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u32 regval;
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dev_dbg(st->dev, "Set tdm, slots:%d width:%d\n", slots, slot_width);
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switch (slot_width) {
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case 32:
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regval = ADAU7118_SLOT_WIDTH(0);
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break;
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case 24:
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regval = ADAU7118_SLOT_WIDTH(2);
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break;
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case 16:
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regval = ADAU7118_SLOT_WIDTH(1);
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break;
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default:
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dev_err(st->dev, "Invalid slot width:%d\n", slot_width);
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return -EINVAL;
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}
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ret = snd_soc_component_update_bits(dai->component,
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ADAU7118_REG_SPT_CTRL1,
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ADAU7118_SLOT_WIDTH_MASK, regval);
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if (ret < 0)
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return ret;
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st->slot_width = slot_width;
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st->slots = slots;
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return 0;
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}
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static int adau7118_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct adau7118_data *st =
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snd_soc_component_get_drvdata(dai->component);
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u32 data_width = params_width(params), slots_width;
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int ret;
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u32 regval;
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if (!st->slots) {
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/* set stereo mode */
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ret = snd_soc_component_update_bits(dai->component,
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ADAU7118_REG_SPT_CTRL1,
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ADAU7118_SAI_MODE_MASK,
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ADAU7118_SAI_MODE(0));
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if (ret < 0)
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return ret;
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slots_width = 32;
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} else {
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slots_width = st->slot_width;
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}
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if (data_width > slots_width) {
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dev_err(st->dev, "Invalid data_width:%d, slots_width:%d",
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data_width, slots_width);
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return -EINVAL;
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}
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if (st->right_j) {
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switch (slots_width - data_width) {
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case 8:
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/* delay bclck by 8 */
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regval = ADAU7118_DATA_FMT(2);
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break;
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case 12:
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/* delay bclck by 12 */
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regval = ADAU7118_DATA_FMT(3);
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break;
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case 16:
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/* delay bclck by 16 */
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regval = ADAU7118_DATA_FMT(4);
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break;
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default:
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dev_err(st->dev,
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"Cannot set right_j setting, slot_w:%d, data_w:%d\n",
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slots_width, data_width);
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return -EINVAL;
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}
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ret = snd_soc_component_update_bits(dai->component,
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ADAU7118_REG_SPT_CTRL1,
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ADAU7118_DATA_FMT_MASK,
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regval);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int adau7118_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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struct adau7118_data *st = snd_soc_component_get_drvdata(component);
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int ret = 0;
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dev_dbg(st->dev, "Set bias level %d\n", level);
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switch (level) {
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case SND_SOC_BIAS_ON:
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case SND_SOC_BIAS_PREPARE:
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break;
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case SND_SOC_BIAS_STANDBY:
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if (snd_soc_component_get_bias_level(component) ==
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SND_SOC_BIAS_OFF) {
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/* power on */
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ret = regulator_enable(st->iovdd);
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if (ret)
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return ret;
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/* there's no timing constraints before enabling dvdd */
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ret = regulator_enable(st->dvdd);
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if (ret) {
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regulator_disable(st->iovdd);
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return ret;
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}
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if (st->hw_mode)
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return 0;
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regcache_cache_only(st->map, false);
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/* sync cache */
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ret = snd_soc_component_cache_sync(component);
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}
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break;
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case SND_SOC_BIAS_OFF:
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/* power off */
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ret = regulator_disable(st->dvdd);
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if (ret)
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return ret;
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ret = regulator_disable(st->iovdd);
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if (ret)
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return ret;
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if (st->hw_mode)
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return 0;
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/* cache only */
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regcache_mark_dirty(st->map);
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regcache_cache_only(st->map, true);
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break;
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}
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return ret;
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}
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static int adau7118_component_probe(struct snd_soc_component *component)
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{
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struct adau7118_data *st = snd_soc_component_get_drvdata(component);
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struct snd_soc_dapm_context *dapm =
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snd_soc_component_get_dapm(component);
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int ret = 0;
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if (st->hw_mode) {
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ret = snd_soc_dapm_new_controls(dapm, adau7118_widgets_hw,
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ARRAY_SIZE(adau7118_widgets_hw));
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if (ret)
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return ret;
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ret = snd_soc_dapm_add_routes(dapm, adau7118_routes_hw,
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ARRAY_SIZE(adau7118_routes_hw));
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} else {
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snd_soc_component_init_regmap(component, st->map);
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ret = snd_soc_dapm_new_controls(dapm, adau7118_widgets_sw,
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ARRAY_SIZE(adau7118_widgets_sw));
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if (ret)
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return ret;
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ret = snd_soc_dapm_add_routes(dapm, adau7118_routes_sw,
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ARRAY_SIZE(adau7118_routes_sw));
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}
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return ret;
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}
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static const struct snd_soc_dai_ops adau7118_ops = {
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.hw_params = adau7118_hw_params,
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.set_channel_map = adau7118_set_channel_map,
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.set_fmt = adau7118_set_fmt,
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.set_tdm_slot = adau7118_set_tdm_slot,
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.set_tristate = adau7118_set_tristate,
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};
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static struct snd_soc_dai_driver adau7118_dai = {
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.name = "adau7118-hifi-capture",
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.capture = {
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.stream_name = "Capture",
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.channels_min = 1,
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.channels_max = 8,
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.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |
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SNDRV_PCM_FMTBIT_S20_LE | SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S24_3LE,
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.rates = SNDRV_PCM_RATE_CONTINUOUS,
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.rate_min = 4000,
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.rate_max = 192000,
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.sig_bits = 24,
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},
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};
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static const struct snd_soc_component_driver adau7118_component_driver = {
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.probe = adau7118_component_probe,
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.set_bias_level = adau7118_set_bias_level,
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.dapm_widgets = adau7118_widgets,
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.num_dapm_widgets = ARRAY_SIZE(adau7118_widgets),
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.use_pmdown_time = 1,
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.endianness = 1,
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.non_legacy_dai_naming = 1,
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};
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static void adau7118_regulator_disable(void *data)
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{
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struct adau7118_data *st = data;
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int ret;
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/*
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* If we fail to disable DVDD, don't bother in trying IOVDD. We
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* actually don't want to be left in the situation where DVDD
|
|
* is enabled and IOVDD is disabled.
|
|
*/
|
|
ret = regulator_disable(st->dvdd);
|
|
if (ret)
|
|
return;
|
|
|
|
regulator_disable(st->iovdd);
|
|
}
|
|
|
|
static int adau7118_regulator_setup(struct adau7118_data *st)
|
|
{
|
|
st->iovdd = devm_regulator_get(st->dev, "iovdd");
|
|
if (IS_ERR(st->iovdd)) {
|
|
dev_err(st->dev, "Could not get iovdd: %ld\n",
|
|
PTR_ERR(st->iovdd));
|
|
return PTR_ERR(st->iovdd);
|
|
}
|
|
|
|
st->dvdd = devm_regulator_get(st->dev, "dvdd");
|
|
if (IS_ERR(st->dvdd)) {
|
|
dev_err(st->dev, "Could not get dvdd: %ld\n",
|
|
PTR_ERR(st->dvdd));
|
|
return PTR_ERR(st->dvdd);
|
|
}
|
|
/* just assume the device is in reset */
|
|
if (!st->hw_mode) {
|
|
regcache_mark_dirty(st->map);
|
|
regcache_cache_only(st->map, true);
|
|
}
|
|
|
|
return devm_add_action_or_reset(st->dev, adau7118_regulator_disable,
|
|
st);
|
|
}
|
|
|
|
static int adau7118_parset_dt(const struct adau7118_data *st)
|
|
{
|
|
int ret;
|
|
u32 dec_ratio = 0;
|
|
/* 4 inputs */
|
|
u32 clk_map[4], regval;
|
|
|
|
if (st->hw_mode)
|
|
return 0;
|
|
|
|
ret = device_property_read_u32(st->dev, "adi,decimation-ratio",
|
|
&dec_ratio);
|
|
if (!ret) {
|
|
switch (dec_ratio) {
|
|
case 64:
|
|
regval = ADAU7118_DEC_RATIO(0);
|
|
break;
|
|
case 32:
|
|
regval = ADAU7118_DEC_RATIO(1);
|
|
break;
|
|
case 16:
|
|
regval = ADAU7118_DEC_RATIO(2);
|
|
break;
|
|
default:
|
|
dev_err(st->dev, "Invalid dec ratio: %u", dec_ratio);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = regmap_update_bits(st->map,
|
|
ADAU7118_REG_DEC_RATIO_CLK_MAP,
|
|
ADAU7118_DEC_RATIO_MASK, regval);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = device_property_read_u32_array(st->dev, "adi,pdm-clk-map",
|
|
clk_map, ARRAY_SIZE(clk_map));
|
|
if (!ret) {
|
|
int pdm;
|
|
u32 _clk_map = 0;
|
|
|
|
for (pdm = 0; pdm < ARRAY_SIZE(clk_map); pdm++)
|
|
_clk_map |= (clk_map[pdm] << (pdm + 4));
|
|
|
|
ret = regmap_update_bits(st->map,
|
|
ADAU7118_REG_DEC_RATIO_CLK_MAP,
|
|
ADAU7118_CLK_MAP_MASK, _clk_map);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int adau7118_probe(struct device *dev, struct regmap *map, bool hw_mode)
|
|
{
|
|
struct adau7118_data *st;
|
|
int ret;
|
|
|
|
st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
|
|
if (!st)
|
|
return -ENOMEM;
|
|
|
|
st->dev = dev;
|
|
st->hw_mode = hw_mode;
|
|
dev_set_drvdata(dev, st);
|
|
|
|
if (!hw_mode) {
|
|
st->map = map;
|
|
adau7118_dai.ops = &adau7118_ops;
|
|
/*
|
|
* Perform a full soft reset. This will set all register's
|
|
* with their reset values.
|
|
*/
|
|
ret = regmap_update_bits(map, ADAU7118_REG_RESET,
|
|
ADAU7118_FULL_SOFT_R_MASK,
|
|
ADAU7118_FULL_SOFT_R(1));
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = adau7118_parset_dt(st);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = adau7118_regulator_setup(st);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return devm_snd_soc_register_component(dev,
|
|
&adau7118_component_driver,
|
|
&adau7118_dai, 1);
|
|
}
|
|
EXPORT_SYMBOL_GPL(adau7118_probe);
|
|
|
|
MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
|
|
MODULE_DESCRIPTION("ADAU7118 8 channel PDM-to-I2S/TDM Converter driver");
|
|
MODULE_LICENSE("GPL");
|