456 lines
14 KiB
C
456 lines
14 KiB
C
/*
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* xHCI host controller driver PCI Bus Glue.
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/acpi.h>
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#include "xhci.h"
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#include "xhci-trace.h"
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#define PORT2_SSIC_CONFIG_REG2 0x883c
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#define PROG_DONE (1 << 30)
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#define SSIC_PORT_UNUSED (1 << 31)
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/* Device for a quirk */
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#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
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#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
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#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
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#define PCI_VENDOR_ID_ETRON 0x1b6f
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#define PCI_DEVICE_ID_EJ168 0x7023
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
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#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
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#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
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static const char hcd_name[] = "xhci_hcd";
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static struct hc_driver __read_mostly xhci_pci_hc_driver;
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static int xhci_pci_setup(struct usb_hcd *hcd);
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static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
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.extra_priv_size = sizeof(struct xhci_hcd),
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.reset = xhci_pci_setup,
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};
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/* called after powerup, by probe or system-pm "wakeup" */
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static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
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{
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/*
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* TODO: Implement finding debug ports later.
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* TODO: see if there are any quirks that need to be added to handle
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* new extended capabilities.
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*/
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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if (!pci_set_mwi(pdev))
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xhci_dbg(xhci, "MWI active\n");
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xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
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return 0;
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}
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static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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/* Look for vendor-specific quirks */
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if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
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(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
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pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
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if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
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pdev->revision == 0x0) {
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xhci->quirks |= XHCI_RESET_EP_QUIRK;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic xHC needs configure"
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" endpoint cmd after reset endpoint");
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}
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if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
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pdev->revision == 0x4) {
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xhci->quirks |= XHCI_SLOW_SUSPEND;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic xHC revision %u"
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"must be suspended extra slowly",
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pdev->revision);
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}
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if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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/* Fresco Logic confirms: all revisions of this chip do not
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* support MSI, even though some of them claim to in their PCI
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* capabilities.
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*/
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xhci->quirks |= XHCI_BROKEN_MSI;
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Fresco Logic revision %u "
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"has broken MSI implementation",
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pdev->revision);
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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}
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if (pdev->vendor == PCI_VENDOR_ID_NEC)
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xhci->quirks |= XHCI_NEC_HOST;
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if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
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xhci->quirks |= XHCI_AMD_0x96_HOST;
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/* AMD PLL quirk */
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if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
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xhci->quirks |= XHCI_AMD_PLL_FIX;
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if (pdev->vendor == PCI_VENDOR_ID_AMD)
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
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xhci->quirks |= XHCI_LPM_SUPPORT;
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xhci->quirks |= XHCI_INTEL_HOST;
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xhci->quirks |= XHCI_AVOID_BEI;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
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xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
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xhci->limit_active_eps = 64;
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xhci->quirks |= XHCI_SW_BW_CHECKING;
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/*
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* PPT desktop boards DH77EB and DH77DF will power back on after
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* a few seconds of being shutdown. The fix for this is to
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* switch the ports from xHCI to EHCI on shutdown. We can't use
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* DMI information to find those particular boards (since each
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* vendor will change the board name), so we have to key off all
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* PPT chipsets.
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*/
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xhci->quirks |= XHCI_SPURIOUS_REBOOT;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
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xhci->quirks |= XHCI_SPURIOUS_REBOOT;
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xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
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}
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
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pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) {
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xhci->quirks |= XHCI_PME_STUCK_QUIRK;
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}
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if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
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pdev->device == PCI_DEVICE_ID_EJ168) {
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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xhci->quirks |= XHCI_TRUST_TX_LENGTH;
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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}
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if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
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pdev->device == 0x0015)
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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if (pdev->vendor == PCI_VENDOR_ID_VIA)
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xhci->quirks |= XHCI_RESET_ON_RESUME;
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/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
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if (pdev->vendor == PCI_VENDOR_ID_VIA &&
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pdev->device == 0x3432)
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
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pdev->device == 0x1042)
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xhci->quirks |= XHCI_BROKEN_STREAMS;
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if (xhci->quirks & XHCI_RESET_ON_RESUME)
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xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
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"QUIRK: Resetting on resume");
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}
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#ifdef CONFIG_ACPI
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static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
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{
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static const u8 intel_dsm_uuid[] = {
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0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
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0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
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};
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union acpi_object *obj;
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obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1,
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NULL);
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ACPI_FREE(obj);
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}
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#else
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static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
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#endif /* CONFIG_ACPI */
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/* called during probe() after chip reset completes */
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static int xhci_pci_setup(struct usb_hcd *hcd)
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{
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struct xhci_hcd *xhci;
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval;
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xhci = hcd_to_xhci(hcd);
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if (!xhci->sbrn)
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pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
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retval = xhci_gen_setup(hcd, xhci_pci_quirks);
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if (retval)
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return retval;
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if (!usb_hcd_is_primary_hcd(hcd))
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return 0;
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xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
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/* Find any debug ports */
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retval = xhci_pci_reinit(xhci, pdev);
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if (!retval)
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return retval;
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return retval;
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}
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/*
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* We need to register our own PCI probe function (instead of the USB core's
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* function) in order to create a second roothub under xHCI.
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*/
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static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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int retval;
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struct xhci_hcd *xhci;
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struct hc_driver *driver;
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struct usb_hcd *hcd;
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driver = (struct hc_driver *)id->driver_data;
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/* Prevent runtime suspending between USB-2 and USB-3 initialization */
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pm_runtime_get_noresume(&dev->dev);
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/* Register the USB 2.0 roothub.
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* FIXME: USB core must know to register the USB 2.0 roothub first.
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* This is sort of silly, because we could just set the HCD driver flags
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* to say USB 2.0, but I'm not sure what the implications would be in
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* the other parts of the HCD code.
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*/
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retval = usb_hcd_pci_probe(dev, id);
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if (retval)
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goto put_runtime_pm;
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/* USB 2.0 roothub is stored in the PCI device now. */
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hcd = dev_get_drvdata(&dev->dev);
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xhci = hcd_to_xhci(hcd);
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xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
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pci_name(dev), hcd);
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if (!xhci->shared_hcd) {
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retval = -ENOMEM;
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goto dealloc_usb2_hcd;
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}
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retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
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IRQF_SHARED);
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if (retval)
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goto put_usb3_hcd;
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/* Roothub already marked as USB 3.0 speed */
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if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
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HCC_MAX_PSA(xhci->hcc_params) >= 4)
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xhci->shared_hcd->can_do_streams = 1;
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if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
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xhci_pme_acpi_rtd3_enable(dev);
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/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
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pm_runtime_put_noidle(&dev->dev);
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return 0;
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put_usb3_hcd:
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usb_put_hcd(xhci->shared_hcd);
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dealloc_usb2_hcd:
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usb_hcd_pci_remove(dev);
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put_runtime_pm:
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pm_runtime_put_noidle(&dev->dev);
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return retval;
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}
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static void xhci_pci_remove(struct pci_dev *dev)
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{
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struct xhci_hcd *xhci;
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xhci = hcd_to_xhci(pci_get_drvdata(dev));
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if (xhci->shared_hcd) {
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usb_remove_hcd(xhci->shared_hcd);
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usb_put_hcd(xhci->shared_hcd);
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}
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usb_hcd_pci_remove(dev);
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/* Workaround for spurious wakeups at shutdown with HSW */
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if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
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pci_set_power_state(dev, PCI_D3hot);
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}
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#ifdef CONFIG_PM
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/*
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* In some Intel xHCI controllers, in order to get D3 working,
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* through a vendor specific SSIC CONFIG register at offset 0x883c,
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* SSIC PORT need to be marked as "unused" before putting xHCI
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* into D3. After D3 exit, the SSIC port need to be marked as "used".
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* Without this change, xHCI might not enter D3 state.
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* Make sure PME works on some Intel xHCI controllers by writing 1 to clear
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* the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
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*/
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static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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u32 val;
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void __iomem *reg;
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if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
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reg = (void __iomem *) xhci->cap_regs + PORT2_SSIC_CONFIG_REG2;
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/* Notify SSIC that SSIC profile programming is not done */
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val = readl(reg) & ~PROG_DONE;
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writel(val, reg);
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/* Mark SSIC port as unused(suspend) or used(resume) */
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val = readl(reg);
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if (suspend)
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val |= SSIC_PORT_UNUSED;
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else
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val &= ~SSIC_PORT_UNUSED;
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writel(val, reg);
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/* Notify SSIC that SSIC profile programming is done */
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val = readl(reg) | PROG_DONE;
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writel(val, reg);
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readl(reg);
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}
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reg = (void __iomem *) xhci->cap_regs + 0x80a4;
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val = readl(reg);
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writel(val | BIT(28), reg);
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readl(reg);
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}
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static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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/*
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* Systems with the TI redriver that loses port status change events
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* need to have the registers polled during D3, so avoid D3cold.
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*/
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if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
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pdev->no_d3cold = true;
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if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
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xhci_pme_quirk(hcd, true);
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return xhci_suspend(xhci, do_wakeup);
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}
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static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval = 0;
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/* The BIOS on systems with the Intel Panther Point chipset may or may
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* not support xHCI natively. That means that during system resume, it
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* may switch the ports back to EHCI so that users can use their
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* keyboard to select a kernel from GRUB after resume from hibernate.
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*
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* The BIOS is supposed to remember whether the OS had xHCI ports
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* enabled before resume, and switch the ports back to xHCI when the
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* BIOS/OS semaphore is written, but we all know we can't trust BIOS
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* writers.
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*
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* Unconditionally switch the ports back to xHCI after a system resume.
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* It should not matter whether the EHCI or xHCI controller is
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* resumed first. It's enough to do the switchover in xHCI because
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* USB core won't notice anything as the hub driver doesn't start
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* running again until after all the devices (including both EHCI and
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* xHCI host controllers) have been resumed.
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*/
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if (pdev->vendor == PCI_VENDOR_ID_INTEL)
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usb_enable_intel_xhci_ports(pdev);
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if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
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xhci_pme_quirk(hcd, false);
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retval = xhci_resume(xhci, hibernated);
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return retval;
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}
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#endif /* CONFIG_PM */
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/*-------------------------------------------------------------------------*/
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/* PCI driver selection metadata; PCI hotplugging uses this */
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static const struct pci_device_id pci_ids[] = { {
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/* handle any USB 3.0 xHCI controller */
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PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
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.driver_data = (unsigned long) &xhci_pci_hc_driver,
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},
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver xhci_pci_driver = {
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.name = (char *) hcd_name,
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.id_table = pci_ids,
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.probe = xhci_pci_probe,
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.remove = xhci_pci_remove,
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/* suspend and resume implemented later */
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.shutdown = usb_hcd_pci_shutdown,
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#ifdef CONFIG_PM
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.driver = {
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.pm = &usb_hcd_pci_pm_ops
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},
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#endif
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};
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static int __init xhci_pci_init(void)
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{
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xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
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#ifdef CONFIG_PM
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xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
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xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
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#endif
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return pci_register_driver(&xhci_pci_driver);
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}
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module_init(xhci_pci_init);
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static void __exit xhci_pci_exit(void)
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{
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pci_unregister_driver(&xhci_pci_driver);
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}
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module_exit(xhci_pci_exit);
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MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
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MODULE_LICENSE("GPL");
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