256 lines
6.6 KiB
C
256 lines
6.6 KiB
C
/*
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* Copyright 2017 Benjamin Herrenschmidt, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#ifndef _KVM_PPC_BOOK3S_XIVE_H
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#define _KVM_PPC_BOOK3S_XIVE_H
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#ifdef CONFIG_KVM_XICS
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#include "book3s_xics.h"
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/*
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* State for one guest irq source.
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*
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* For each guest source we allocate a HW interrupt in the XIVE
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* which we use for all SW triggers. It will be unused for
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* pass-through but it's easier to keep around as the same
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* guest interrupt can alternatively be emulated or pass-through
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* if a physical device is hot unplugged and replaced with an
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* emulated one.
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*
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* This state structure is very similar to the XICS one with
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* additional XIVE specific tracking.
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*/
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struct kvmppc_xive_irq_state {
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bool valid; /* Interrupt entry is valid */
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u32 number; /* Guest IRQ number */
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u32 ipi_number; /* XIVE IPI HW number */
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struct xive_irq_data ipi_data; /* XIVE IPI associated data */
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u32 pt_number; /* XIVE Pass-through number if any */
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struct xive_irq_data *pt_data; /* XIVE Pass-through associated data */
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/* Targetting as set by guest */
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u8 guest_priority; /* Guest set priority */
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u8 saved_priority; /* Saved priority when masking */
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/* Actual targetting */
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u32 act_server; /* Actual server */
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u8 act_priority; /* Actual priority */
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/* Various state bits */
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bool in_eoi; /* Synchronize with H_EOI */
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bool old_p; /* P bit state when masking */
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bool old_q; /* Q bit state when masking */
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bool lsi; /* level-sensitive interrupt */
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bool asserted; /* Only for emulated LSI: current state */
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/* Saved for migration state */
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bool in_queue;
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bool saved_p;
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bool saved_q;
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u8 saved_scan_prio;
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};
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/* Select the "right" interrupt (IPI vs. passthrough) */
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static inline void kvmppc_xive_select_irq(struct kvmppc_xive_irq_state *state,
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u32 *out_hw_irq,
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struct xive_irq_data **out_xd)
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{
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if (state->pt_number) {
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if (out_hw_irq)
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*out_hw_irq = state->pt_number;
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if (out_xd)
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*out_xd = state->pt_data;
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} else {
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if (out_hw_irq)
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*out_hw_irq = state->ipi_number;
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if (out_xd)
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*out_xd = &state->ipi_data;
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}
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}
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/*
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* This corresponds to an "ICS" in XICS terminology, we use it
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* as a mean to break up source information into multiple structures.
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*/
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struct kvmppc_xive_src_block {
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arch_spinlock_t lock;
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u16 id;
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struct kvmppc_xive_irq_state irq_state[KVMPPC_XICS_IRQ_PER_ICS];
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};
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struct kvmppc_xive {
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struct kvm *kvm;
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struct kvm_device *dev;
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struct dentry *dentry;
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/* VP block associated with the VM */
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u32 vp_base;
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/* Blocks of sources */
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struct kvmppc_xive_src_block *src_blocks[KVMPPC_XICS_MAX_ICS_ID + 1];
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u32 max_sbid;
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/*
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* For state save, we lazily scan the queues on the first interrupt
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* being migrated. We don't have a clean way to reset that flags
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* so we keep track of the number of valid sources and how many of
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* them were migrated so we can reset when all of them have been
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* processed.
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*/
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u32 src_count;
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u32 saved_src_count;
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/*
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* Some irqs are delayed on restore until the source is created,
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* keep track here of how many of them
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*/
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u32 delayed_irqs;
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/* Which queues (priorities) are in use by the guest */
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u8 qmap;
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/* Queue orders */
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u32 q_order;
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u32 q_page_order;
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};
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#define KVMPPC_XIVE_Q_COUNT 8
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struct kvmppc_xive_vcpu {
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struct kvmppc_xive *xive;
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struct kvm_vcpu *vcpu;
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bool valid;
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/* Server number. This is the HW CPU ID from a guest perspective */
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u32 server_num;
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/*
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* HW VP corresponding to this VCPU. This is the base of the VP
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* block plus the server number.
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*/
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u32 vp_id;
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u32 vp_chip_id;
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u32 vp_cam;
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/* IPI used for sending ... IPIs */
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u32 vp_ipi;
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struct xive_irq_data vp_ipi_data;
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/* Local emulation state */
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uint8_t cppr; /* guest CPPR */
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uint8_t hw_cppr;/* Hardware CPPR */
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uint8_t mfrr;
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uint8_t pending;
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/* Each VP has 8 queues though we only provision some */
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struct xive_q queues[KVMPPC_XIVE_Q_COUNT];
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u32 esc_virq[KVMPPC_XIVE_Q_COUNT];
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char *esc_virq_names[KVMPPC_XIVE_Q_COUNT];
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/* Stash a delayed irq on restore from migration (see set_icp) */
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u32 delayed_irq;
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/* Stats */
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u64 stat_rm_h_xirr;
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u64 stat_rm_h_ipoll;
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u64 stat_rm_h_cppr;
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u64 stat_rm_h_eoi;
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u64 stat_rm_h_ipi;
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u64 stat_vm_h_xirr;
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u64 stat_vm_h_ipoll;
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u64 stat_vm_h_cppr;
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u64 stat_vm_h_eoi;
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u64 stat_vm_h_ipi;
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};
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static inline struct kvm_vcpu *kvmppc_xive_find_server(struct kvm *kvm, u32 nr)
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{
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struct kvm_vcpu *vcpu = NULL;
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int i;
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (vcpu->arch.xive_vcpu && nr == vcpu->arch.xive_vcpu->server_num)
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return vcpu;
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}
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return NULL;
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}
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static inline struct kvmppc_xive_src_block *kvmppc_xive_find_source(struct kvmppc_xive *xive,
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u32 irq, u16 *source)
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{
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u32 bid = irq >> KVMPPC_XICS_ICS_SHIFT;
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u16 src = irq & KVMPPC_XICS_SRC_MASK;
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if (source)
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*source = src;
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if (bid > KVMPPC_XICS_MAX_ICS_ID)
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return NULL;
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return xive->src_blocks[bid];
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}
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/*
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* Mapping between guest priorities and host priorities
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* is as follow.
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*
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* Guest request for 0...6 are honored. Guest request for anything
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* higher results in a priority of 7 being applied.
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*
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* However, when XIRR is returned via H_XIRR, 7 is translated to 0xb
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* in order to match AIX expectations
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*
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* Similar mapping is done for CPPR values
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*/
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static inline u8 xive_prio_from_guest(u8 prio)
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{
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if (prio == 0xff || prio < 8)
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return prio;
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return 7;
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}
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static inline u8 xive_prio_to_guest(u8 prio)
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{
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if (prio == 0xff || prio < 7)
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return prio;
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return 0xb;
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}
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static inline u32 __xive_read_eq(__be32 *qpage, u32 msk, u32 *idx, u32 *toggle)
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{
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u32 cur;
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if (!qpage)
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return 0;
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cur = be32_to_cpup(qpage + *idx);
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if ((cur >> 31) == *toggle)
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return 0;
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*idx = (*idx + 1) & msk;
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if (*idx == 0)
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(*toggle) ^= 1;
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return cur & 0x7fffffff;
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}
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extern unsigned long xive_rm_h_xirr(struct kvm_vcpu *vcpu);
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extern unsigned long xive_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server);
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extern int xive_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
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unsigned long mfrr);
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extern int xive_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr);
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extern int xive_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr);
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extern unsigned long (*__xive_vm_h_xirr)(struct kvm_vcpu *vcpu);
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extern unsigned long (*__xive_vm_h_ipoll)(struct kvm_vcpu *vcpu, unsigned long server);
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extern int (*__xive_vm_h_ipi)(struct kvm_vcpu *vcpu, unsigned long server,
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unsigned long mfrr);
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extern int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr);
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extern int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr);
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#endif /* CONFIG_KVM_XICS */
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#endif /* _KVM_PPC_BOOK3S_XICS_H */
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