Dave Jiang ce17ad0d54 cxl: Wait Memory_Info_Valid before access memory related info ... The Memory_Info_Valid bit (CXL 3.0 8.1.3.8.2) indicates that the CXL Range Size High and Size Low registers are valid. The bit must be set within 1 second of reset deassertion to the device. Check valid bit before we check the Memory_Active bit when waiting for cxl_await_media_ready() to ensure that the memory info is valid for consumption. Also ensures both DVSEC ranges 1 and 2 are ready if DVSEC Capability indicates they are both supported. Fixes: 523e594d9c ("cxl/pci: Implement wait for media active") Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/168444687469.3134781.11033518965387297327.stgit@djiang5-mobl3 Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2023-05-18 16:42:41 -07:00
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core	cxl: Wait Memory_Info_Valid before access memory related info	2023-05-18 16:42:41 -07:00
Kconfig	Merge branch 'for-6.3/cxl-ram-region' into cxl/next	2023-02-10 18:11:01 -08:00
Makefile	cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation	2022-11-30 16:30:47 -08:00
acpi.c	Merge branch 'for-6.3/cxl-ram-region' into cxl/next	2023-02-10 18:11:01 -08:00
cxl.h	cxl/port: Enable the HDM decoder capability for switch ports	2023-05-18 13:18:49 -07:00
cxlmem.h	cxl/mbox: Update CMD_RC_TABLE	2023-04-23 12:10:26 -07:00
cxlpci.h	cxl: Wait Memory_Info_Valid before access memory related info	2023-05-18 16:42:41 -07:00
mem.c	cxl/mem: Add debugfs attributes for poison inject and clear	2023-04-23 12:08:39 -07:00
pci.c	Merge branch 'for-6.4/cxl-poison' into for-6.4/cxl	2023-04-23 12:09:56 -07:00
pmem.c	cxl/pmem: Fix nvdimm registration races	2023-02-13 17:01:05 -08:00
port.c	cxl/port: Enable the HDM decoder capability for switch ports	2023-05-18 13:18:49 -07:00
security.c	cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size	2022-12-06 14:36:02 -08:00