443 lines
12 KiB
ReStructuredText
443 lines
12 KiB
ReStructuredText
.. include:: <isonum.txt>
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==========================
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Linux generic IRQ handling
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==========================
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:Copyright: |copy| 2005-2010: Thomas Gleixner
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:Copyright: |copy| 2005-2006: Ingo Molnar
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Introduction
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============
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The generic interrupt handling layer is designed to provide a complete
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abstraction of interrupt handling for device drivers. It is able to
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handle all the different types of interrupt controller hardware. Device
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drivers use generic API functions to request, enable, disable and free
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interrupts. The drivers do not have to know anything about interrupt
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hardware details, so they can be used on different platforms without
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code changes.
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This documentation is provided to developers who want to implement an
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interrupt subsystem based for their architecture, with the help of the
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generic IRQ handling layer.
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Rationale
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=========
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The original implementation of interrupt handling in Linux uses the
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__do_IRQ() super-handler, which is able to deal with every type of
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interrupt logic.
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Originally, Russell King identified different types of handlers to build
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a quite universal set for the ARM interrupt handler implementation in
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Linux 2.5/2.6. He distinguished between:
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- Level type
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- Edge type
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- Simple type
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During the implementation we identified another type:
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- Fast EOI type
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In the SMP world of the __do_IRQ() super-handler another type was
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identified:
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- Per CPU type
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This split implementation of high-level IRQ handlers allows us to
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optimize the flow of the interrupt handling for each specific interrupt
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type. This reduces complexity in that particular code path and allows
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the optimized handling of a given type.
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The original general IRQ implementation used hw_interrupt_type
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structures and their ``->ack``, ``->end`` [etc.] callbacks to differentiate
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the flow control in the super-handler. This leads to a mix of flow logic
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and low-level hardware logic, and it also leads to unnecessary code
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duplication: for example in i386, there is an ``ioapic_level_irq`` and an
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``ioapic_edge_irq`` IRQ-type which share many of the low-level details but
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have different flow handling.
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A more natural abstraction is the clean separation of the 'irq flow' and
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the 'chip details'.
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Analysing a couple of architecture's IRQ subsystem implementations
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reveals that most of them can use a generic set of 'irq flow' methods
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and only need to add the chip-level specific code. The separation is
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also valuable for (sub)architectures which need specific quirks in the
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IRQ flow itself but not in the chip details - and thus provides a more
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transparent IRQ subsystem design.
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Each interrupt descriptor is assigned its own high-level flow handler,
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which is normally one of the generic implementations. (This high-level
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flow handler implementation also makes it simple to provide
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demultiplexing handlers which can be found in embedded platforms on
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various architectures.)
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The separation makes the generic interrupt handling layer more flexible
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and extensible. For example, an (sub)architecture can use a generic
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IRQ-flow implementation for 'level type' interrupts and add a
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(sub)architecture specific 'edge type' implementation.
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To make the transition to the new model easier and prevent the breakage
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of existing implementations, the __do_IRQ() super-handler is still
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available. This leads to a kind of duality for the time being. Over time
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the new model should be used in more and more architectures, as it
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enables smaller and cleaner IRQ subsystems. It's deprecated for three
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years now and about to be removed.
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Known Bugs And Assumptions
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==========================
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None (knock on wood).
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Abstraction layers
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==================
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There are three main levels of abstraction in the interrupt code:
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1. High-level driver API
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2. High-level IRQ flow handlers
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3. Chip-level hardware encapsulation
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Interrupt control flow
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----------------------
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Each interrupt is described by an interrupt descriptor structure
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irq_desc. The interrupt is referenced by an 'unsigned int' numeric
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value which selects the corresponding interrupt description structure in
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the descriptor structures array. The descriptor structure contains
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status information and pointers to the interrupt flow method and the
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interrupt chip structure which are assigned to this interrupt.
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Whenever an interrupt triggers, the low-level architecture code calls
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into the generic interrupt code by calling desc->handle_irq(). This
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high-level IRQ handling function only uses desc->irq_data.chip
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primitives referenced by the assigned chip descriptor structure.
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High-level Driver API
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---------------------
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The high-level Driver API consists of following functions:
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- request_irq()
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- request_threaded_irq()
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- free_irq()
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- disable_irq()
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- enable_irq()
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- disable_irq_nosync() (SMP only)
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- synchronize_irq() (SMP only)
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- irq_set_irq_type()
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- irq_set_irq_wake()
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- irq_set_handler_data()
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- irq_set_chip()
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- irq_set_chip_data()
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See the autogenerated function documentation for details.
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High-level IRQ flow handlers
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----------------------------
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The generic layer provides a set of pre-defined irq-flow methods:
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- handle_level_irq()
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- handle_edge_irq()
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- handle_fasteoi_irq()
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- handle_simple_irq()
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- handle_percpu_irq()
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- handle_edge_eoi_irq()
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- handle_bad_irq()
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The interrupt flow handlers (either pre-defined or architecture
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specific) are assigned to specific interrupts by the architecture either
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during bootup or during device initialization.
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Default flow implementations
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Helper functions
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^^^^^^^^^^^^^^^^
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The helper functions call the chip primitives and are used by the
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default flow implementations. The following helper functions are
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implemented (simplified excerpt)::
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default_enable(struct irq_data *data)
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{
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desc->irq_data.chip->irq_unmask(data);
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}
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default_disable(struct irq_data *data)
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{
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if (!delay_disable(data))
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desc->irq_data.chip->irq_mask(data);
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}
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default_ack(struct irq_data *data)
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{
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chip->irq_ack(data);
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}
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default_mask_ack(struct irq_data *data)
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{
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if (chip->irq_mask_ack) {
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chip->irq_mask_ack(data);
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} else {
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chip->irq_mask(data);
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chip->irq_ack(data);
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}
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}
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noop(struct irq_data *data))
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{
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}
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Default flow handler implementations
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Default Level IRQ flow handler
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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handle_level_irq provides a generic implementation for level-triggered
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interrupts.
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The following control flow is implemented (simplified excerpt)::
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desc->irq_data.chip->irq_mask_ack();
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handle_irq_event(desc->action);
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desc->irq_data.chip->irq_unmask();
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Default Fast EOI IRQ flow handler
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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handle_fasteoi_irq provides a generic implementation for interrupts,
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which only need an EOI at the end of the handler.
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The following control flow is implemented (simplified excerpt)::
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handle_irq_event(desc->action);
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desc->irq_data.chip->irq_eoi();
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Default Edge IRQ flow handler
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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handle_edge_irq provides a generic implementation for edge-triggered
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interrupts.
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The following control flow is implemented (simplified excerpt)::
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if (desc->status & running) {
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desc->irq_data.chip->irq_mask_ack();
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desc->status |= pending | masked;
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return;
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}
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desc->irq_data.chip->irq_ack();
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desc->status |= running;
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do {
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if (desc->status & masked)
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desc->irq_data.chip->irq_unmask();
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desc->status &= ~pending;
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handle_irq_event(desc->action);
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} while (status & pending);
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desc->status &= ~running;
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Default simple IRQ flow handler
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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handle_simple_irq provides a generic implementation for simple
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interrupts.
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.. note::
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The simple flow handler does not call any handler/chip primitives.
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The following control flow is implemented (simplified excerpt)::
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handle_irq_event(desc->action);
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Default per CPU flow handler
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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handle_percpu_irq provides a generic implementation for per CPU
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interrupts.
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Per CPU interrupts are only available on SMP and the handler provides a
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simplified version without locking.
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The following control flow is implemented (simplified excerpt)::
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if (desc->irq_data.chip->irq_ack)
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desc->irq_data.chip->irq_ack();
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handle_irq_event(desc->action);
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if (desc->irq_data.chip->irq_eoi)
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desc->irq_data.chip->irq_eoi();
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EOI Edge IRQ flow handler
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^^^^^^^^^^^^^^^^^^^^^^^^^
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handle_edge_eoi_irq provides an abnomination of the edge handler
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which is solely used to tame a badly wreckaged irq controller on
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powerpc/cell.
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Bad IRQ flow handler
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^^^^^^^^^^^^^^^^^^^^
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handle_bad_irq is used for spurious interrupts which have no real
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handler assigned..
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Quirks and optimizations
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~~~~~~~~~~~~~~~~~~~~~~~~
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The generic functions are intended for 'clean' architectures and chips,
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which have no platform-specific IRQ handling quirks. If an architecture
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needs to implement quirks on the 'flow' level then it can do so by
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overriding the high-level irq-flow handler.
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Delayed interrupt disable
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~~~~~~~~~~~~~~~~~~~~~~~~~
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This per interrupt selectable feature, which was introduced by Russell
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King in the ARM interrupt implementation, does not mask an interrupt at
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the hardware level when disable_irq() is called. The interrupt is kept
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enabled and is masked in the flow handler when an interrupt event
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happens. This prevents losing edge interrupts on hardware which does not
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store an edge interrupt event while the interrupt is disabled at the
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hardware level. When an interrupt arrives while the IRQ_DISABLED flag
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is set, then the interrupt is masked at the hardware level and the
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IRQ_PENDING bit is set. When the interrupt is re-enabled by
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enable_irq() the pending bit is checked and if it is set, the interrupt
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is resent either via hardware or by a software resend mechanism. (It's
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necessary to enable CONFIG_HARDIRQS_SW_RESEND when you want to use
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the delayed interrupt disable feature and your hardware is not capable
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of retriggering an interrupt.) The delayed interrupt disable is not
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configurable.
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Chip-level hardware encapsulation
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---------------------------------
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The chip-level hardware descriptor structure :c:type:`irq_chip` contains all
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the direct chip relevant functions, which can be utilized by the irq flow
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implementations.
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- ``irq_ack``
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- ``irq_mask_ack`` - Optional, recommended for performance
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- ``irq_mask``
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- ``irq_unmask``
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- ``irq_eoi`` - Optional, required for EOI flow handlers
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- ``irq_retrigger`` - Optional
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- ``irq_set_type`` - Optional
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- ``irq_set_wake`` - Optional
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These primitives are strictly intended to mean what they say: ack means
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ACK, masking means masking of an IRQ line, etc. It is up to the flow
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handler(s) to use these basic units of low-level functionality.
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__do_IRQ entry point
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====================
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The original implementation __do_IRQ() was an alternative entry point
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for all types of interrupts. It no longer exists.
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This handler turned out to be not suitable for all interrupt hardware
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and was therefore reimplemented with split functionality for
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edge/level/simple/percpu interrupts. This is not only a functional
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optimization. It also shortens code paths for interrupts.
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Locking on SMP
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==============
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The locking of chip registers is up to the architecture that defines the
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chip primitives. The per-irq structure is protected via desc->lock, by
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the generic layer.
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Generic interrupt chip
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======================
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To avoid copies of identical implementations of IRQ chips the core
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provides a configurable generic interrupt chip implementation.
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Developers should check carefully whether the generic chip fits their
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needs before implementing the same functionality slightly differently
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themselves.
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.. kernel-doc:: kernel/irq/generic-chip.c
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:export:
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Structures
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==========
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This chapter contains the autogenerated documentation of the structures
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which are used in the generic IRQ layer.
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.. kernel-doc:: include/linux/irq.h
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:internal:
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.. kernel-doc:: include/linux/interrupt.h
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:internal:
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Public Functions Provided
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=========================
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This chapter contains the autogenerated documentation of the kernel API
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functions which are exported.
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.. kernel-doc:: kernel/irq/manage.c
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.. kernel-doc:: kernel/irq/chip.c
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Internal Functions Provided
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===========================
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This chapter contains the autogenerated documentation of the internal
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functions.
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.. kernel-doc:: kernel/irq/irqdesc.c
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.. kernel-doc:: kernel/irq/handle.c
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.. kernel-doc:: kernel/irq/chip.c
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Credits
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=======
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The following people have contributed to this document:
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1. Thomas Gleixner tglx@linutronix.de
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2. Ingo Molnar mingo@elte.hu
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