166 lines
3.6 KiB
ArmAsm
166 lines
3.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/sysreg.h>
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#include <asm/virt.h>
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.text
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.pushsection .hyp.idmap.text, "ax"
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.align 11
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ENTRY(__kvm_hyp_init)
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ventry __invalid // Synchronous EL2t
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ventry __invalid // IRQ EL2t
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ventry __invalid // FIQ EL2t
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ventry __invalid // Error EL2t
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ventry __invalid // Synchronous EL2h
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ventry __invalid // IRQ EL2h
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ventry __invalid // FIQ EL2h
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ventry __invalid // Error EL2h
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ventry __do_hyp_init // Synchronous 64-bit EL1
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ventry __invalid // IRQ 64-bit EL1
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ventry __invalid // FIQ 64-bit EL1
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ventry __invalid // Error 64-bit EL1
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ventry __invalid // Synchronous 32-bit EL1
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ventry __invalid // IRQ 32-bit EL1
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ventry __invalid // FIQ 32-bit EL1
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ventry __invalid // Error 32-bit EL1
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__invalid:
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b .
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/*
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* x0: HYP pgd
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* x1: HYP stack
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* x2: HYP vectors
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* x3: per-CPU offset
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*/
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__do_hyp_init:
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/* Check for a stub HVC call */
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cmp x0, #HVC_STUB_HCALL_NR
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b.lo __kvm_handle_stub_hvc
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phys_to_ttbr x4, x0
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alternative_if ARM64_HAS_CNP
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orr x4, x4, #TTBR_CNP_BIT
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alternative_else_nop_endif
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msr ttbr0_el2, x4
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mrs x4, tcr_el1
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ldr x5, =TCR_EL2_MASK
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and x4, x4, x5
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mov x5, #TCR_EL2_RES1
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orr x4, x4, x5
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/*
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* The ID map may be configured to use an extended virtual address
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* range. This is only the case if system RAM is out of range for the
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* currently configured page size and VA_BITS, in which case we will
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* also need the extended virtual range for the HYP ID map, or we won't
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* be able to enable the EL2 MMU.
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*
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* However, at EL2, there is only one TTBR register, and we can't switch
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* between translation tables *and* update TCR_EL2.T0SZ at the same
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* time. Bottom line: we need to use the extended range with *both* our
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* translation tables.
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*
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* So use the same T0SZ value we use for the ID map.
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*/
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ldr_l x5, idmap_t0sz
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bfi x4, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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/*
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* Set the PS bits in TCR_EL2.
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*/
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tcr_compute_pa_size x4, #TCR_EL2_PS_SHIFT, x5, x6
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msr tcr_el2, x4
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mrs x4, mair_el1
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msr mair_el2, x4
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isb
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/* Invalidate the stale TLBs from Bootloader */
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tlbi alle2
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dsb sy
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/*
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* Preserve all the RES1 bits while setting the default flags,
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* as well as the EE bit on BE. Drop the A flag since the compiler
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* is allowed to generate unaligned accesses.
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*/
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ldr x4, =(SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A))
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CPU_BE( orr x4, x4, #SCTLR_ELx_EE)
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msr sctlr_el2, x4
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isb
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/* Set the stack and new vectors */
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kern_hyp_va x1
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mov sp, x1
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msr vbar_el2, x2
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/* Set tpidr_el2 for use by HYP */
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msr tpidr_el2, x3
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/* Hello, World! */
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eret
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ENDPROC(__kvm_hyp_init)
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ENTRY(__kvm_handle_stub_hvc)
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cmp x0, #HVC_SOFT_RESTART
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b.ne 1f
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/* This is where we're about to jump, staying at EL2 */
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msr elr_el2, x1
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mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL2h)
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msr spsr_el2, x0
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/* Shuffle the arguments, and don't come back */
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mov x0, x2
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mov x1, x3
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mov x2, x4
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b reset
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1: cmp x0, #HVC_RESET_VECTORS
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b.ne 1f
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reset:
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/*
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* Reset kvm back to the hyp stub. Do not clobber x0-x4 in
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* case we coming via HVC_SOFT_RESTART.
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*/
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mrs x5, sctlr_el2
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ldr x6, =SCTLR_ELx_FLAGS
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bic x5, x5, x6 // Clear SCTL_M and etc
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pre_disable_mmu_workaround
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msr sctlr_el2, x5
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isb
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/* Install stub vectors */
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adr_l x5, __hyp_stub_vectors
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msr vbar_el2, x5
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mov x0, xzr
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eret
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1: /* Bad stub call */
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ldr x0, =HVC_STUB_ERR
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eret
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ENDPROC(__kvm_handle_stub_hvc)
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.ltorg
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.popsection
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