564 lines
14 KiB
C
564 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020-21 Intel Corporation.
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*/
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#include <linux/acpi.h>
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <net/rtnetlink.h>
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#include "iosm_ipc_imem.h"
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#include "iosm_ipc_pcie.h"
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#include "iosm_ipc_protocol.h"
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MODULE_DESCRIPTION("IOSM Driver");
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MODULE_LICENSE("GPL v2");
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/* WWAN GUID */
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static guid_t wwan_acpi_guid = GUID_INIT(0xbad01b75, 0x22a8, 0x4f48, 0x87, 0x92,
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0xbd, 0xde, 0x94, 0x67, 0x74, 0x7d);
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static void ipc_pcie_resources_release(struct iosm_pcie *ipc_pcie)
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{
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/* Free the MSI resources. */
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ipc_release_irq(ipc_pcie);
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/* Free mapped doorbell scratchpad bus memory into CPU space. */
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iounmap(ipc_pcie->scratchpad);
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/* Free mapped IPC_REGS bus memory into CPU space. */
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iounmap(ipc_pcie->ipc_regs);
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/* Releases all PCI I/O and memory resources previously reserved by a
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* successful call to pci_request_regions. Call this function only
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* after all use of the PCI regions has ceased.
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*/
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pci_release_regions(ipc_pcie->pci);
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}
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static void ipc_pcie_cleanup(struct iosm_pcie *ipc_pcie)
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{
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/* Free the shared memory resources. */
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ipc_imem_cleanup(ipc_pcie->imem);
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ipc_pcie_resources_release(ipc_pcie);
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/* Signal to the system that the PCI device is not in use. */
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pci_disable_device(ipc_pcie->pci);
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}
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static void ipc_pcie_deinit(struct iosm_pcie *ipc_pcie)
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{
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kfree(ipc_pcie->imem);
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kfree(ipc_pcie);
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}
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static void ipc_pcie_remove(struct pci_dev *pci)
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{
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struct iosm_pcie *ipc_pcie = pci_get_drvdata(pci);
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ipc_pcie_cleanup(ipc_pcie);
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ipc_pcie_deinit(ipc_pcie);
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}
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static int ipc_pcie_resources_request(struct iosm_pcie *ipc_pcie)
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{
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struct pci_dev *pci = ipc_pcie->pci;
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u32 cap = 0;
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u32 ret;
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/* Reserved PCI I/O and memory resources.
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* Mark all PCI regions associated with PCI device pci as
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* being reserved by owner IOSM_IPC.
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*/
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ret = pci_request_regions(pci, "IOSM_IPC");
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if (ret) {
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dev_err(ipc_pcie->dev, "failed pci request regions");
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goto pci_request_region_fail;
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}
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/* Reserve the doorbell IPC REGS memory resources.
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* Remap the memory into CPU space. Arrange for the physical address
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* (BAR) to be visible from this driver.
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* pci_ioremap_bar() ensures that the memory is marked uncachable.
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*/
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ipc_pcie->ipc_regs = pci_ioremap_bar(pci, ipc_pcie->ipc_regs_bar_nr);
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if (!ipc_pcie->ipc_regs) {
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dev_err(ipc_pcie->dev, "IPC REGS ioremap error");
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ret = -EBUSY;
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goto ipc_regs_remap_fail;
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}
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/* Reserve the MMIO scratchpad memory resources.
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* Remap the memory into CPU space. Arrange for the physical address
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* (BAR) to be visible from this driver.
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* pci_ioremap_bar() ensures that the memory is marked uncachable.
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*/
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ipc_pcie->scratchpad =
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pci_ioremap_bar(pci, ipc_pcie->scratchpad_bar_nr);
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if (!ipc_pcie->scratchpad) {
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dev_err(ipc_pcie->dev, "doorbell scratchpad ioremap error");
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ret = -EBUSY;
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goto scratch_remap_fail;
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}
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/* Install the irq handler triggered by CP. */
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ret = ipc_acquire_irq(ipc_pcie);
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if (ret) {
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dev_err(ipc_pcie->dev, "acquiring MSI irq failed!");
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goto irq_acquire_fail;
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}
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/* Enable bus-mastering for the IOSM IPC device. */
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pci_set_master(pci);
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/* Enable LTR if possible
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* This is needed for L1.2!
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*/
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pcie_capability_read_dword(ipc_pcie->pci, PCI_EXP_DEVCAP2, &cap);
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if (cap & PCI_EXP_DEVCAP2_LTR)
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pcie_capability_set_word(ipc_pcie->pci, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_LTR_EN);
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dev_dbg(ipc_pcie->dev, "link between AP and CP is fully on");
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return ret;
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irq_acquire_fail:
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iounmap(ipc_pcie->scratchpad);
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scratch_remap_fail:
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iounmap(ipc_pcie->ipc_regs);
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ipc_regs_remap_fail:
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pci_release_regions(pci);
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pci_request_region_fail:
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return ret;
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}
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bool ipc_pcie_check_aspm_enabled(struct iosm_pcie *ipc_pcie,
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bool parent)
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{
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struct pci_dev *pdev;
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u16 value = 0;
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u32 enabled;
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if (parent)
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pdev = ipc_pcie->pci->bus->self;
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else
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pdev = ipc_pcie->pci;
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pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &value);
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enabled = value & PCI_EXP_LNKCTL_ASPMC;
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dev_dbg(ipc_pcie->dev, "ASPM L1: 0x%04X 0x%03X", pdev->device, value);
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return (enabled == PCI_EXP_LNKCTL_ASPM_L1 ||
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enabled == PCI_EXP_LNKCTL_ASPMC);
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}
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bool ipc_pcie_check_data_link_active(struct iosm_pcie *ipc_pcie)
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{
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struct pci_dev *parent;
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u16 link_status = 0;
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if (!ipc_pcie->pci->bus || !ipc_pcie->pci->bus->self) {
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dev_err(ipc_pcie->dev, "root port not found");
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return false;
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}
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parent = ipc_pcie->pci->bus->self;
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pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &link_status);
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dev_dbg(ipc_pcie->dev, "Link status: 0x%04X", link_status);
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return link_status & PCI_EXP_LNKSTA_DLLLA;
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}
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static bool ipc_pcie_check_aspm_supported(struct iosm_pcie *ipc_pcie,
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bool parent)
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{
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struct pci_dev *pdev;
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u32 support;
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u32 cap = 0;
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if (parent)
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pdev = ipc_pcie->pci->bus->self;
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else
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pdev = ipc_pcie->pci;
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pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &cap);
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support = u32_get_bits(cap, PCI_EXP_LNKCAP_ASPMS);
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if (support < PCI_EXP_LNKCTL_ASPM_L1) {
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dev_dbg(ipc_pcie->dev, "ASPM L1 not supported: 0x%04X",
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pdev->device);
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return false;
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}
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return true;
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}
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void ipc_pcie_config_aspm(struct iosm_pcie *ipc_pcie)
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{
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bool parent_aspm_enabled, dev_aspm_enabled;
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/* check if both root port and child supports ASPM L1 */
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if (!ipc_pcie_check_aspm_supported(ipc_pcie, true) ||
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!ipc_pcie_check_aspm_supported(ipc_pcie, false))
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return;
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parent_aspm_enabled = ipc_pcie_check_aspm_enabled(ipc_pcie, true);
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dev_aspm_enabled = ipc_pcie_check_aspm_enabled(ipc_pcie, false);
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dev_dbg(ipc_pcie->dev, "ASPM parent: %s device: %s",
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parent_aspm_enabled ? "Enabled" : "Disabled",
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dev_aspm_enabled ? "Enabled" : "Disabled");
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}
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/* Initializes PCIe endpoint configuration */
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static void ipc_pcie_config_init(struct iosm_pcie *ipc_pcie)
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{
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/* BAR0 is used for doorbell */
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ipc_pcie->ipc_regs_bar_nr = IPC_DOORBELL_BAR0;
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/* update HW configuration */
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ipc_pcie->scratchpad_bar_nr = IPC_SCRATCHPAD_BAR2;
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ipc_pcie->doorbell_reg_offset = IPC_DOORBELL_CH_OFFSET;
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ipc_pcie->doorbell_write = IPC_WRITE_PTR_REG_0;
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ipc_pcie->doorbell_capture = IPC_CAPTURE_PTR_REG_0;
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}
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/* This will read the BIOS WWAN RTD3 settings:
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* D0L1.2/D3L2/Disabled
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*/
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static enum ipc_pcie_sleep_state ipc_pcie_read_bios_cfg(struct device *dev)
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{
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union acpi_object *object;
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acpi_handle handle_acpi;
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handle_acpi = ACPI_HANDLE(dev);
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if (!handle_acpi) {
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pr_debug("pci device is NOT ACPI supporting device\n");
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goto default_ret;
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}
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object = acpi_evaluate_dsm(handle_acpi, &wwan_acpi_guid, 0, 3, NULL);
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if (object && object->integer.value == 3)
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return IPC_PCIE_D3L2;
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default_ret:
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return IPC_PCIE_D0L12;
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}
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static int ipc_pcie_probe(struct pci_dev *pci,
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const struct pci_device_id *pci_id)
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{
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struct iosm_pcie *ipc_pcie = kzalloc(sizeof(*ipc_pcie), GFP_KERNEL);
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pr_debug("Probing device 0x%X from the vendor 0x%X", pci_id->device,
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pci_id->vendor);
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if (!ipc_pcie)
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goto ret_fail;
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/* Initialize ipc dbg component for the PCIe device */
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ipc_pcie->dev = &pci->dev;
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/* Set the driver specific data. */
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pci_set_drvdata(pci, ipc_pcie);
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/* Save the address of the PCI device configuration. */
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ipc_pcie->pci = pci;
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/* Update platform configuration */
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ipc_pcie_config_init(ipc_pcie);
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/* Initialize the device before it is used. Ask low-level code
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* to enable I/O and memory. Wake up the device if it was suspended.
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*/
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if (pci_enable_device(pci)) {
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dev_err(ipc_pcie->dev, "failed to enable the AP PCIe device");
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/* If enable of PCIe device has failed then calling
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* ipc_pcie_cleanup will panic the system. More over
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* ipc_pcie_cleanup() is required to be called after
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* ipc_imem_mount()
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*/
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goto pci_enable_fail;
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}
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ipc_pcie_config_aspm(ipc_pcie);
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dev_dbg(ipc_pcie->dev, "PCIe device enabled.");
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/* Read WWAN RTD3 BIOS Setting
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*/
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ipc_pcie->d3l2_support = ipc_pcie_read_bios_cfg(&pci->dev);
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ipc_pcie->suspend = 0;
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if (ipc_pcie_resources_request(ipc_pcie))
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goto resources_req_fail;
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/* Establish the link to the imem layer. */
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ipc_pcie->imem = ipc_imem_init(ipc_pcie, pci->device,
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ipc_pcie->scratchpad, ipc_pcie->dev);
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if (!ipc_pcie->imem) {
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dev_err(ipc_pcie->dev, "failed to init imem");
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goto imem_init_fail;
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}
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return 0;
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imem_init_fail:
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ipc_pcie_resources_release(ipc_pcie);
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resources_req_fail:
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pci_disable_device(pci);
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pci_enable_fail:
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kfree(ipc_pcie);
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ret_fail:
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return -EIO;
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}
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static const struct pci_device_id iosm_ipc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, INTEL_CP_DEVICE_7560_ID) },
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{}
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};
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MODULE_DEVICE_TABLE(pci, iosm_ipc_ids);
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/* Enter sleep in s2idle case
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*/
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static int __maybe_unused ipc_pcie_suspend_s2idle(struct iosm_pcie *ipc_pcie)
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{
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ipc_cp_irq_sleep_control(ipc_pcie, IPC_MEM_DEV_PM_FORCE_SLEEP);
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/* Complete all memory stores before setting bit */
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smp_mb__before_atomic();
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set_bit(0, &ipc_pcie->suspend);
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/* Complete all memory stores after setting bit */
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smp_mb__after_atomic();
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ipc_imem_pm_s2idle_sleep(ipc_pcie->imem, true);
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return 0;
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}
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/* Resume from sleep in s2idle case
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*/
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static int __maybe_unused ipc_pcie_resume_s2idle(struct iosm_pcie *ipc_pcie)
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{
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ipc_cp_irq_sleep_control(ipc_pcie, IPC_MEM_DEV_PM_FORCE_ACTIVE);
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ipc_imem_pm_s2idle_sleep(ipc_pcie->imem, false);
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/* Complete all memory stores before clearing bit. */
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smp_mb__before_atomic();
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clear_bit(0, &ipc_pcie->suspend);
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/* Complete all memory stores after clearing bit. */
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smp_mb__after_atomic();
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return 0;
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}
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int __maybe_unused ipc_pcie_suspend(struct iosm_pcie *ipc_pcie)
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{
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struct pci_dev *pdev;
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int ret;
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pdev = ipc_pcie->pci;
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/* Execute D3 one time. */
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if (pdev->current_state != PCI_D0) {
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dev_dbg(ipc_pcie->dev, "done for PM=%d", pdev->current_state);
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return 0;
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}
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/* The HAL shall ask the shared memory layer whether D3 is allowed. */
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ipc_imem_pm_suspend(ipc_pcie->imem);
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/* Save the PCI configuration space of a device before suspending. */
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ret = pci_save_state(pdev);
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if (ret) {
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dev_err(ipc_pcie->dev, "pci_save_state error=%d", ret);
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return ret;
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}
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/* Set the power state of a PCI device.
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* Transition a device to a new power state, using the device's PCI PM
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* registers.
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*/
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ret = pci_set_power_state(pdev, PCI_D3cold);
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if (ret) {
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dev_err(ipc_pcie->dev, "pci_set_power_state error=%d", ret);
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return ret;
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}
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dev_dbg(ipc_pcie->dev, "SUSPEND done");
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return ret;
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}
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int __maybe_unused ipc_pcie_resume(struct iosm_pcie *ipc_pcie)
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{
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int ret;
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/* Set the power state of a PCI device.
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* Transition a device to a new power state, using the device's PCI PM
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* registers.
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*/
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ret = pci_set_power_state(ipc_pcie->pci, PCI_D0);
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if (ret) {
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dev_err(ipc_pcie->dev, "pci_set_power_state error=%d", ret);
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return ret;
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}
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pci_restore_state(ipc_pcie->pci);
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/* The HAL shall inform the shared memory layer that the device is
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* active.
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*/
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ipc_imem_pm_resume(ipc_pcie->imem);
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dev_dbg(ipc_pcie->dev, "RESUME done");
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return ret;
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}
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static int __maybe_unused ipc_pcie_suspend_cb(struct device *dev)
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{
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struct iosm_pcie *ipc_pcie;
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struct pci_dev *pdev;
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pdev = to_pci_dev(dev);
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ipc_pcie = pci_get_drvdata(pdev);
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switch (ipc_pcie->d3l2_support) {
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case IPC_PCIE_D0L12:
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ipc_pcie_suspend_s2idle(ipc_pcie);
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break;
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case IPC_PCIE_D3L2:
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ipc_pcie_suspend(ipc_pcie);
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break;
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}
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return 0;
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}
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static int __maybe_unused ipc_pcie_resume_cb(struct device *dev)
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{
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struct iosm_pcie *ipc_pcie;
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struct pci_dev *pdev;
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pdev = to_pci_dev(dev);
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ipc_pcie = pci_get_drvdata(pdev);
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switch (ipc_pcie->d3l2_support) {
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case IPC_PCIE_D0L12:
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ipc_pcie_resume_s2idle(ipc_pcie);
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break;
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case IPC_PCIE_D3L2:
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ipc_pcie_resume(ipc_pcie);
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break;
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}
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(iosm_ipc_pm, ipc_pcie_suspend_cb, ipc_pcie_resume_cb);
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static struct pci_driver iosm_ipc_driver = {
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.name = KBUILD_MODNAME,
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.probe = ipc_pcie_probe,
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.remove = ipc_pcie_remove,
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.driver = {
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.pm = &iosm_ipc_pm,
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},
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.id_table = iosm_ipc_ids,
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};
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module_pci_driver(iosm_ipc_driver);
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int ipc_pcie_addr_map(struct iosm_pcie *ipc_pcie, unsigned char *data,
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size_t size, dma_addr_t *mapping, int direction)
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{
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if (ipc_pcie->pci) {
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*mapping = dma_map_single(&ipc_pcie->pci->dev, data, size,
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direction);
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if (dma_mapping_error(&ipc_pcie->pci->dev, *mapping)) {
|
|
dev_err(ipc_pcie->dev, "dma mapping failed");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void ipc_pcie_addr_unmap(struct iosm_pcie *ipc_pcie, size_t size,
|
|
dma_addr_t mapping, int direction)
|
|
{
|
|
if (!mapping)
|
|
return;
|
|
if (ipc_pcie->pci)
|
|
dma_unmap_single(&ipc_pcie->pci->dev, mapping, size, direction);
|
|
}
|
|
|
|
struct sk_buff *ipc_pcie_alloc_local_skb(struct iosm_pcie *ipc_pcie,
|
|
gfp_t flags, size_t size)
|
|
{
|
|
struct sk_buff *skb;
|
|
|
|
if (!ipc_pcie || !size) {
|
|
pr_err("invalid pcie object or size");
|
|
return NULL;
|
|
}
|
|
|
|
skb = __netdev_alloc_skb(NULL, size, flags);
|
|
if (!skb)
|
|
return NULL;
|
|
|
|
IPC_CB(skb)->op_type = (u8)UL_DEFAULT;
|
|
IPC_CB(skb)->mapping = 0;
|
|
|
|
return skb;
|
|
}
|
|
|
|
struct sk_buff *ipc_pcie_alloc_skb(struct iosm_pcie *ipc_pcie, size_t size,
|
|
gfp_t flags, dma_addr_t *mapping,
|
|
int direction, size_t headroom)
|
|
{
|
|
struct sk_buff *skb = ipc_pcie_alloc_local_skb(ipc_pcie, flags,
|
|
size + headroom);
|
|
if (!skb)
|
|
return NULL;
|
|
|
|
if (headroom)
|
|
skb_reserve(skb, headroom);
|
|
|
|
if (ipc_pcie_addr_map(ipc_pcie, skb->data, size, mapping, direction)) {
|
|
dev_kfree_skb(skb);
|
|
return NULL;
|
|
}
|
|
|
|
BUILD_BUG_ON(sizeof(*IPC_CB(skb)) > sizeof(skb->cb));
|
|
|
|
/* Store the mapping address in skb scratch pad for later usage */
|
|
IPC_CB(skb)->mapping = *mapping;
|
|
IPC_CB(skb)->direction = direction;
|
|
IPC_CB(skb)->len = size;
|
|
|
|
return skb;
|
|
}
|
|
|
|
void ipc_pcie_kfree_skb(struct iosm_pcie *ipc_pcie, struct sk_buff *skb)
|
|
{
|
|
if (!skb)
|
|
return;
|
|
|
|
ipc_pcie_addr_unmap(ipc_pcie, IPC_CB(skb)->len, IPC_CB(skb)->mapping,
|
|
IPC_CB(skb)->direction);
|
|
IPC_CB(skb)->mapping = 0;
|
|
dev_kfree_skb(skb);
|
|
}
|