261 lines
7.6 KiB
C
261 lines
7.6 KiB
C
/*
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* intel_mid_dma_regs.h - Intel MID DMA Drivers
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*
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* Copyright (C) 2008-10 Intel Corp
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* Author: Vinod Koul <vinod.koul@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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*
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*/
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#ifndef __INTEL_MID_DMAC_REGS_H__
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#define __INTEL_MID_DMAC_REGS_H__
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#include <linux/dmaengine.h>
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#include <linux/dmapool.h>
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#include <linux/pci_ids.h>
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#define INTEL_MID_DMA_DRIVER_VERSION "1.0.5"
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#define REG_BIT0 0x00000001
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#define REG_BIT8 0x00000100
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#define UNMASK_INTR_REG(chan_num) \
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((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num))
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#define MASK_INTR_REG(chan_num) (REG_BIT8 << chan_num)
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#define ENABLE_CHANNEL(chan_num) \
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((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num))
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#define DESCS_PER_CHANNEL 16
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/*DMA Registers*/
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/*registers associated with channel programming*/
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#define DMA_REG_SIZE 0x400
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#define DMA_CH_SIZE 0x58
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/*CH X REG = (DMA_CH_SIZE)*CH_NO + REG*/
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#define SAR 0x00 /* Source Address Register*/
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#define DAR 0x08 /* Destination Address Register*/
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#define CTL_LOW 0x18 /* Control Register*/
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#define CTL_HIGH 0x1C /* Control Register*/
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#define CFG_LOW 0x40 /* Configuration Register Low*/
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#define CFG_HIGH 0x44 /* Configuration Register high*/
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#define STATUS_TFR 0x2E8
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#define STATUS_BLOCK 0x2F0
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#define STATUS_ERR 0x308
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#define RAW_TFR 0x2C0
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#define RAW_BLOCK 0x2C8
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#define RAW_ERR 0x2E0
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#define MASK_TFR 0x310
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#define MASK_BLOCK 0x318
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#define MASK_SRC_TRAN 0x320
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#define MASK_DST_TRAN 0x328
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#define MASK_ERR 0x330
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#define CLEAR_TFR 0x338
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#define CLEAR_BLOCK 0x340
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#define CLEAR_SRC_TRAN 0x348
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#define CLEAR_DST_TRAN 0x350
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#define CLEAR_ERR 0x358
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#define INTR_STATUS 0x360
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#define DMA_CFG 0x398
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#define DMA_CHAN_EN 0x3A0
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/*DMA channel control registers*/
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union intel_mid_dma_ctl_lo {
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struct {
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u32 int_en:1; /*enable or disable interrupts*/
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/*should be 0*/
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u32 dst_tr_width:3; /*destination transfer width*/
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/*usually 32 bits = 010*/
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u32 src_tr_width:3; /*source transfer width*/
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/*usually 32 bits = 010*/
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u32 dinc:2; /*destination address inc/dec*/
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/*For mem:INC=00, Periphral NoINC=11*/
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u32 sinc:2; /*source address inc or dec, as above*/
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u32 dst_msize:3; /*destination burst transaction length*/
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/*always = 16 ie 011*/
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u32 src_msize:3; /*source burst transaction length*/
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/*always = 16 ie 011*/
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u32 reser1:3;
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u32 tt_fc:3; /*transfer type and flow controller*/
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/*M-M = 000
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P-M = 010
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M-P = 001*/
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u32 dms:2; /*destination master select = 0*/
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u32 sms:2; /*source master select = 0*/
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u32 llp_dst_en:1; /*enable/disable destination LLP = 0*/
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u32 llp_src_en:1; /*enable/disable source LLP = 0*/
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u32 reser2:3;
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} ctlx;
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u32 ctl_lo;
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};
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union intel_mid_dma_ctl_hi {
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struct {
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u32 block_ts:12; /*block transfer size*/
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/*configured by DMAC*/
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u32 reser:20;
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} ctlx;
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u32 ctl_hi;
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};
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/*DMA channel configuration registers*/
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union intel_mid_dma_cfg_lo {
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struct {
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u32 reser1:5;
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u32 ch_prior:3; /*channel priority = 0*/
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u32 ch_susp:1; /*channel suspend = 0*/
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u32 fifo_empty:1; /*FIFO empty or not R bit = 0*/
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u32 hs_sel_dst:1; /*select HW/SW destn handshaking*/
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/*HW = 0, SW = 1*/
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u32 hs_sel_src:1; /*select HW/SW src handshaking*/
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u32 reser2:6;
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u32 dst_hs_pol:1; /*dest HS interface polarity*/
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u32 src_hs_pol:1; /*src HS interface polarity*/
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u32 max_abrst:10; /*max AMBA burst len = 0 (no sw limit*/
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u32 reload_src:1; /*auto reload src addr =1 if src is P*/
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u32 reload_dst:1; /*AR destn addr =1 if dstn is P*/
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} cfgx;
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u32 cfg_lo;
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};
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union intel_mid_dma_cfg_hi {
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struct {
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u32 fcmode:1; /*flow control mode = 1*/
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u32 fifo_mode:1; /*FIFO mode select = 1*/
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u32 protctl:3; /*protection control = 0*/
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u32 rsvd:2;
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u32 src_per:4; /*src hw HS interface*/
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u32 dst_per:4; /*dstn hw HS interface*/
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u32 reser2:17;
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} cfgx;
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u32 cfg_hi;
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};
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/**
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* struct intel_mid_dma_chan - internal mid representation of a DMA channel
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* @chan: dma_chan strcture represetation for mid chan
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* @ch_regs: MMIO register space pointer to channel register
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* @dma_base: MMIO register space DMA engine base pointer
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* @ch_id: DMA channel id
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* @lock: channel spinlock
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* @completed: DMA cookie
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* @active_list: current active descriptors
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* @queue: current queued up descriptors
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* @free_list: current free descriptors
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* @slave: dma slave struture
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* @descs_allocated: total number of decsiptors allocated
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* @dma: dma device struture pointer
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* @in_use: bool representing if ch is in use or not
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*/
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struct intel_mid_dma_chan {
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struct dma_chan chan;
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void __iomem *ch_regs;
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void __iomem *dma_base;
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int ch_id;
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spinlock_t lock;
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dma_cookie_t completed;
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struct list_head active_list;
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struct list_head queue;
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struct list_head free_list;
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struct intel_mid_dma_slave *slave;
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unsigned int descs_allocated;
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struct middma_device *dma;
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bool in_use;
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};
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static inline struct intel_mid_dma_chan *to_intel_mid_dma_chan(
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struct dma_chan *chan)
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{
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return container_of(chan, struct intel_mid_dma_chan, chan);
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}
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/**
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* struct middma_device - internal representation of a DMA device
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* @pdev: PCI device
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* @dma_base: MMIO register space pointer of DMA
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* @dma_pool: for allocating DMA descriptors
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* @common: embedded struct dma_device
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* @tasklet: dma tasklet for processing interrupts
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* @ch: per channel data
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* @pci_id: DMA device PCI ID
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* @intr_mask: Interrupt mask to be used
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* @mask_reg: MMIO register for periphral mask
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* @chan_base: Base ch index (read from driver data)
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* @max_chan: max number of chs supported (from drv_data)
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* @block_size: Block size of DMA transfer supported (from drv_data)
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* @pimr_mask: MMIO register addr for periphral interrupt (from drv_data)
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*/
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struct middma_device {
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struct pci_dev *pdev;
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void __iomem *dma_base;
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struct pci_pool *dma_pool;
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struct dma_device common;
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struct tasklet_struct tasklet;
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struct intel_mid_dma_chan ch[MAX_CHAN];
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unsigned int pci_id;
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unsigned int intr_mask;
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void __iomem *mask_reg;
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int chan_base;
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int max_chan;
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int block_size;
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unsigned int pimr_mask;
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};
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static inline struct middma_device *to_middma_device(struct dma_device *common)
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{
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return container_of(common, struct middma_device, common);
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}
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struct intel_mid_dma_desc {
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void __iomem *block; /*ch ptr*/
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struct list_head desc_node;
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struct dma_async_tx_descriptor txd;
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size_t len;
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dma_addr_t sar;
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dma_addr_t dar;
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u32 cfg_hi;
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u32 cfg_lo;
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u32 ctl_lo;
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u32 ctl_hi;
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dma_addr_t next;
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enum dma_data_direction dirn;
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enum dma_status status;
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enum intel_mid_dma_width width; /*width of DMA txn*/
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enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
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};
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static inline int test_ch_en(void __iomem *dma, u32 ch_no)
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{
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u32 en_reg = ioread32(dma + DMA_CHAN_EN);
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return (en_reg >> ch_no) & 0x1;
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}
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static inline struct intel_mid_dma_desc *to_intel_mid_dma_desc
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(struct dma_async_tx_descriptor *txd)
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{
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return container_of(txd, struct intel_mid_dma_desc, txd);
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}
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#endif /*__INTEL_MID_DMAC_REGS_H__*/
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