857 lines
23 KiB
C
857 lines
23 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2010 - 2012 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2010 - 2012 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#include <linux/export.h>
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#include <net/netlink.h>
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#include "iwl-io.h"
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#include "iwl-fh.h"
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#include "iwl-prph.h"
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#include "iwl-trans.h"
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#include "iwl-test.h"
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#include "iwl-csr.h"
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#include "iwl-testmode.h"
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/*
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* Periphery registers absolute lower bound. This is used in order to
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* differentiate registery access through HBUS_TARG_PRPH_* and
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* HBUS_TARG_MEM_* accesses.
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*/
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#define IWL_ABS_PRPH_START (0xA00000)
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/*
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* The TLVs used in the gnl message policy between the kernel module and
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* user space application. iwl_testmode_gnl_msg_policy is to be carried
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* through the NL80211_CMD_TESTMODE channel regulated by nl80211.
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* See iwl-testmode.h
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*/
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static
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struct nla_policy iwl_testmode_gnl_msg_policy[IWL_TM_ATTR_MAX] = {
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[IWL_TM_ATTR_COMMAND] = { .type = NLA_U32, },
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[IWL_TM_ATTR_UCODE_CMD_ID] = { .type = NLA_U8, },
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[IWL_TM_ATTR_UCODE_CMD_DATA] = { .type = NLA_UNSPEC, },
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[IWL_TM_ATTR_REG_OFFSET] = { .type = NLA_U32, },
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[IWL_TM_ATTR_REG_VALUE8] = { .type = NLA_U8, },
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[IWL_TM_ATTR_REG_VALUE32] = { .type = NLA_U32, },
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[IWL_TM_ATTR_SYNC_RSP] = { .type = NLA_UNSPEC, },
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[IWL_TM_ATTR_UCODE_RX_PKT] = { .type = NLA_UNSPEC, },
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[IWL_TM_ATTR_EEPROM] = { .type = NLA_UNSPEC, },
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[IWL_TM_ATTR_TRACE_ADDR] = { .type = NLA_UNSPEC, },
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[IWL_TM_ATTR_TRACE_DUMP] = { .type = NLA_UNSPEC, },
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[IWL_TM_ATTR_TRACE_SIZE] = { .type = NLA_U32, },
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[IWL_TM_ATTR_FIXRATE] = { .type = NLA_U32, },
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[IWL_TM_ATTR_UCODE_OWNER] = { .type = NLA_U8, },
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[IWL_TM_ATTR_MEM_ADDR] = { .type = NLA_U32, },
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[IWL_TM_ATTR_BUFFER_SIZE] = { .type = NLA_U32, },
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[IWL_TM_ATTR_BUFFER_DUMP] = { .type = NLA_UNSPEC, },
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[IWL_TM_ATTR_FW_VERSION] = { .type = NLA_U32, },
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[IWL_TM_ATTR_DEVICE_ID] = { .type = NLA_U32, },
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[IWL_TM_ATTR_FW_TYPE] = { .type = NLA_U32, },
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[IWL_TM_ATTR_FW_INST_SIZE] = { .type = NLA_U32, },
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[IWL_TM_ATTR_FW_DATA_SIZE] = { .type = NLA_U32, },
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[IWL_TM_ATTR_ENABLE_NOTIFICATION] = {.type = NLA_FLAG, },
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};
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static inline void iwl_test_trace_clear(struct iwl_test *tst)
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{
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memset(&tst->trace, 0, sizeof(struct iwl_test_trace));
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}
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static void iwl_test_trace_stop(struct iwl_test *tst)
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{
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if (!tst->trace.enabled)
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return;
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if (tst->trace.cpu_addr && tst->trace.dma_addr)
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dma_free_coherent(tst->trans->dev,
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tst->trace.tsize,
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tst->trace.cpu_addr,
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tst->trace.dma_addr);
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iwl_test_trace_clear(tst);
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}
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static inline void iwl_test_mem_clear(struct iwl_test *tst)
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{
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memset(&tst->mem, 0, sizeof(struct iwl_test_mem));
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}
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static inline void iwl_test_mem_stop(struct iwl_test *tst)
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{
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if (!tst->mem.in_read)
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return;
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iwl_test_mem_clear(tst);
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}
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/*
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* Initializes the test object
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* During the lifetime of the test object it is assumed that the transport is
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* started. The test object should be stopped before the transport is stopped.
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*/
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void iwl_test_init(struct iwl_test *tst, struct iwl_trans *trans,
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struct iwl_test_ops *ops)
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{
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tst->trans = trans;
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tst->ops = ops;
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iwl_test_trace_clear(tst);
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iwl_test_mem_clear(tst);
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}
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EXPORT_SYMBOL_GPL(iwl_test_init);
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/*
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* Stop the test object
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*/
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void iwl_test_free(struct iwl_test *tst)
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{
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iwl_test_mem_stop(tst);
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iwl_test_trace_stop(tst);
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}
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EXPORT_SYMBOL_GPL(iwl_test_free);
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static inline int iwl_test_send_cmd(struct iwl_test *tst,
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struct iwl_host_cmd *cmd)
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{
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return tst->ops->send_cmd(tst->trans->op_mode, cmd);
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}
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static inline bool iwl_test_valid_hw_addr(struct iwl_test *tst, u32 addr)
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{
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return tst->ops->valid_hw_addr(addr);
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}
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static inline u32 iwl_test_fw_ver(struct iwl_test *tst)
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{
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return tst->ops->get_fw_ver(tst->trans->op_mode);
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}
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static inline struct sk_buff*
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iwl_test_alloc_reply(struct iwl_test *tst, int len)
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{
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return tst->ops->alloc_reply(tst->trans->op_mode, len);
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}
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static inline int iwl_test_reply(struct iwl_test *tst, struct sk_buff *skb)
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{
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return tst->ops->reply(tst->trans->op_mode, skb);
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}
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static inline struct sk_buff*
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iwl_test_alloc_event(struct iwl_test *tst, int len)
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{
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return tst->ops->alloc_event(tst->trans->op_mode, len);
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}
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static inline void
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iwl_test_event(struct iwl_test *tst, struct sk_buff *skb)
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{
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return tst->ops->event(tst->trans->op_mode, skb);
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}
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/*
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* This function handles the user application commands to the fw. The fw
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* commands are sent in a synchronuous manner. In case that the user requested
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* to get commands response, it is send to the user.
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*/
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static int iwl_test_fw_cmd(struct iwl_test *tst, struct nlattr **tb)
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{
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struct iwl_host_cmd cmd;
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struct iwl_rx_packet *pkt;
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struct sk_buff *skb;
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void *reply_buf;
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u32 reply_len;
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int ret;
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bool cmd_want_skb;
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memset(&cmd, 0, sizeof(struct iwl_host_cmd));
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if (!tb[IWL_TM_ATTR_UCODE_CMD_ID] ||
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!tb[IWL_TM_ATTR_UCODE_CMD_DATA]) {
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IWL_ERR(tst->trans, "Missing fw command mandatory fields\n");
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return -ENOMSG;
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}
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cmd.flags = CMD_ON_DEMAND | CMD_SYNC;
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cmd_want_skb = nla_get_flag(tb[IWL_TM_ATTR_UCODE_CMD_SKB]);
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if (cmd_want_skb)
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cmd.flags |= CMD_WANT_SKB;
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cmd.id = nla_get_u8(tb[IWL_TM_ATTR_UCODE_CMD_ID]);
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cmd.data[0] = nla_data(tb[IWL_TM_ATTR_UCODE_CMD_DATA]);
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cmd.len[0] = nla_len(tb[IWL_TM_ATTR_UCODE_CMD_DATA]);
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cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
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IWL_DEBUG_INFO(tst->trans, "test fw cmd=0x%x, flags 0x%x, len %d\n",
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cmd.id, cmd.flags, cmd.len[0]);
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ret = iwl_test_send_cmd(tst, &cmd);
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if (ret) {
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IWL_ERR(tst->trans, "Failed to send hcmd\n");
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return ret;
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}
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if (!cmd_want_skb)
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return ret;
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/* Handling return of SKB to the user */
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pkt = cmd.resp_pkt;
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if (!pkt) {
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IWL_ERR(tst->trans, "HCMD received a null response packet\n");
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return ret;
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}
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reply_len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
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skb = iwl_test_alloc_reply(tst, reply_len + 20);
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reply_buf = kmalloc(reply_len, GFP_KERNEL);
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if (!skb || !reply_buf) {
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kfree_skb(skb);
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kfree(reply_buf);
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return -ENOMEM;
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}
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/* The reply is in a page, that we cannot send to user space. */
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memcpy(reply_buf, &(pkt->hdr), reply_len);
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iwl_free_resp(&cmd);
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if (nla_put_u32(skb, IWL_TM_ATTR_COMMAND,
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IWL_TM_CMD_DEV2APP_UCODE_RX_PKT) ||
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nla_put(skb, IWL_TM_ATTR_UCODE_RX_PKT, reply_len, reply_buf))
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goto nla_put_failure;
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return iwl_test_reply(tst, skb);
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nla_put_failure:
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IWL_DEBUG_INFO(tst->trans, "Failed creating NL attributes\n");
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kfree(reply_buf);
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kfree_skb(skb);
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return -ENOMSG;
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}
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/*
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* Handles the user application commands for register access.
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*/
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static int iwl_test_reg(struct iwl_test *tst, struct nlattr **tb)
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{
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u32 ofs, val32, cmd;
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u8 val8;
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struct sk_buff *skb;
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int status = 0;
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struct iwl_trans *trans = tst->trans;
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if (!tb[IWL_TM_ATTR_REG_OFFSET]) {
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IWL_ERR(trans, "Missing reg offset\n");
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return -ENOMSG;
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}
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ofs = nla_get_u32(tb[IWL_TM_ATTR_REG_OFFSET]);
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IWL_DEBUG_INFO(trans, "test reg access cmd offset=0x%x\n", ofs);
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cmd = nla_get_u32(tb[IWL_TM_ATTR_COMMAND]);
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/*
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* Allow access only to FH/CSR/HBUS in direct mode.
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* Since we don't have the upper bounds for the CSR and HBUS segments,
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* we will use only the upper bound of FH for sanity check.
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*/
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if (ofs >= FH_MEM_UPPER_BOUND) {
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IWL_ERR(trans, "offset out of segment (0x0 - 0x%x)\n",
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FH_MEM_UPPER_BOUND);
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return -EINVAL;
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}
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switch (cmd) {
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32:
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val32 = iwl_read_direct32(tst->trans, ofs);
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IWL_DEBUG_INFO(trans, "32 value to read 0x%x\n", val32);
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skb = iwl_test_alloc_reply(tst, 20);
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if (!skb) {
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IWL_ERR(trans, "Memory allocation fail\n");
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return -ENOMEM;
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}
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if (nla_put_u32(skb, IWL_TM_ATTR_REG_VALUE32, val32))
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goto nla_put_failure;
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status = iwl_test_reply(tst, skb);
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if (status < 0)
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IWL_ERR(trans, "Error sending msg : %d\n", status);
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break;
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE32:
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if (!tb[IWL_TM_ATTR_REG_VALUE32]) {
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IWL_ERR(trans, "Missing value to write\n");
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return -ENOMSG;
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} else {
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val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]);
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IWL_DEBUG_INFO(trans, "32b write val=0x%x\n", val32);
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iwl_write_direct32(tst->trans, ofs, val32);
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}
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break;
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case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8:
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if (!tb[IWL_TM_ATTR_REG_VALUE8]) {
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IWL_ERR(trans, "Missing value to write\n");
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return -ENOMSG;
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} else {
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val8 = nla_get_u8(tb[IWL_TM_ATTR_REG_VALUE8]);
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IWL_DEBUG_INFO(trans, "8b write val=0x%x\n", val8);
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iwl_write8(tst->trans, ofs, val8);
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}
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break;
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default:
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IWL_ERR(trans, "Unknown test register cmd ID\n");
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return -ENOMSG;
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}
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return status;
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nla_put_failure:
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kfree_skb(skb);
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return -EMSGSIZE;
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}
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/*
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* Handles the request to start FW tracing. Allocates of the trace buffer
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* and sends a reply to user space with the address of the allocated buffer.
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*/
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static int iwl_test_trace_begin(struct iwl_test *tst, struct nlattr **tb)
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{
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struct sk_buff *skb;
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int status = 0;
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if (tst->trace.enabled)
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return -EBUSY;
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if (!tb[IWL_TM_ATTR_TRACE_SIZE])
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tst->trace.size = TRACE_BUFF_SIZE_DEF;
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else
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tst->trace.size =
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nla_get_u32(tb[IWL_TM_ATTR_TRACE_SIZE]);
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if (!tst->trace.size)
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return -EINVAL;
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if (tst->trace.size < TRACE_BUFF_SIZE_MIN ||
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tst->trace.size > TRACE_BUFF_SIZE_MAX)
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return -EINVAL;
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tst->trace.tsize = tst->trace.size + TRACE_BUFF_PADD;
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tst->trace.cpu_addr = dma_alloc_coherent(tst->trans->dev,
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tst->trace.tsize,
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&tst->trace.dma_addr,
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GFP_KERNEL);
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if (!tst->trace.cpu_addr)
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return -ENOMEM;
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tst->trace.enabled = true;
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tst->trace.trace_addr = (u8 *)PTR_ALIGN(tst->trace.cpu_addr, 0x100);
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memset(tst->trace.trace_addr, 0x03B, tst->trace.size);
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skb = iwl_test_alloc_reply(tst, sizeof(tst->trace.dma_addr) + 20);
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if (!skb) {
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IWL_ERR(tst->trans, "Memory allocation fail\n");
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iwl_test_trace_stop(tst);
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return -ENOMEM;
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}
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if (nla_put(skb, IWL_TM_ATTR_TRACE_ADDR,
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sizeof(tst->trace.dma_addr),
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(u64 *)&tst->trace.dma_addr))
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goto nla_put_failure;
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status = iwl_test_reply(tst, skb);
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if (status < 0)
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IWL_ERR(tst->trans, "Error sending msg : %d\n", status);
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tst->trace.nchunks = DIV_ROUND_UP(tst->trace.size,
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DUMP_CHUNK_SIZE);
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return status;
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nla_put_failure:
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kfree_skb(skb);
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if (nla_get_u32(tb[IWL_TM_ATTR_COMMAND]) ==
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IWL_TM_CMD_APP2DEV_BEGIN_TRACE)
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iwl_test_trace_stop(tst);
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return -EMSGSIZE;
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}
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/*
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* Handles indirect read from the periphery or the SRAM. The read is performed
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* to a temporary buffer. The user space application should later issue a dump
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*/
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static int iwl_test_indirect_read(struct iwl_test *tst, u32 addr, u32 size)
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{
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struct iwl_trans *trans = tst->trans;
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unsigned long flags;
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int i;
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if (size & 0x3)
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return -EINVAL;
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tst->mem.size = size;
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tst->mem.addr = kmalloc(tst->mem.size, GFP_KERNEL);
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if (tst->mem.addr == NULL)
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return -ENOMEM;
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/* Hard-coded periphery absolute address */
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if (IWL_ABS_PRPH_START <= addr &&
|
|
addr < IWL_ABS_PRPH_START + PRPH_END) {
|
|
spin_lock_irqsave(&trans->reg_lock, flags);
|
|
iwl_grab_nic_access(trans);
|
|
iwl_write32(trans, HBUS_TARG_PRPH_RADDR,
|
|
addr | (3 << 24));
|
|
for (i = 0; i < size; i += 4)
|
|
*(u32 *)(tst->mem.addr + i) =
|
|
iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
|
|
iwl_release_nic_access(trans);
|
|
spin_unlock_irqrestore(&trans->reg_lock, flags);
|
|
} else { /* target memory (SRAM) */
|
|
_iwl_read_targ_mem_dwords(trans, addr,
|
|
tst->mem.addr,
|
|
tst->mem.size / 4);
|
|
}
|
|
|
|
tst->mem.nchunks =
|
|
DIV_ROUND_UP(tst->mem.size, DUMP_CHUNK_SIZE);
|
|
tst->mem.in_read = true;
|
|
return 0;
|
|
|
|
}
|
|
|
|
/*
|
|
* Handles indirect write to the periphery or SRAM. The is performed to a
|
|
* temporary buffer.
|
|
*/
|
|
static int iwl_test_indirect_write(struct iwl_test *tst, u32 addr,
|
|
u32 size, unsigned char *buf)
|
|
{
|
|
struct iwl_trans *trans = tst->trans;
|
|
u32 val, i;
|
|
unsigned long flags;
|
|
|
|
if (IWL_ABS_PRPH_START <= addr &&
|
|
addr < IWL_ABS_PRPH_START + PRPH_END) {
|
|
/* Periphery writes can be 1-3 bytes long, or DWORDs */
|
|
if (size < 4) {
|
|
memcpy(&val, buf, size);
|
|
spin_lock_irqsave(&trans->reg_lock, flags);
|
|
iwl_grab_nic_access(trans);
|
|
iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
|
|
(addr & 0x0000FFFF) |
|
|
((size - 1) << 24));
|
|
iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
|
|
iwl_release_nic_access(trans);
|
|
/* needed after consecutive writes w/o read */
|
|
mmiowb();
|
|
spin_unlock_irqrestore(&trans->reg_lock, flags);
|
|
} else {
|
|
if (size % 4)
|
|
return -EINVAL;
|
|
for (i = 0; i < size; i += 4)
|
|
iwl_write_prph(trans, addr+i,
|
|
*(u32 *)(buf+i));
|
|
}
|
|
} else if (iwl_test_valid_hw_addr(tst, addr)) {
|
|
_iwl_write_targ_mem_dwords(trans, addr, buf, size / 4);
|
|
} else {
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Handles the user application commands for indirect read/write
|
|
* to/from the periphery or the SRAM.
|
|
*/
|
|
static int iwl_test_indirect_mem(struct iwl_test *tst, struct nlattr **tb)
|
|
{
|
|
u32 addr, size, cmd;
|
|
unsigned char *buf;
|
|
|
|
/* Both read and write should be blocked, for atomicity */
|
|
if (tst->mem.in_read)
|
|
return -EBUSY;
|
|
|
|
cmd = nla_get_u32(tb[IWL_TM_ATTR_COMMAND]);
|
|
if (!tb[IWL_TM_ATTR_MEM_ADDR]) {
|
|
IWL_ERR(tst->trans, "Error finding memory offset address\n");
|
|
return -ENOMSG;
|
|
}
|
|
addr = nla_get_u32(tb[IWL_TM_ATTR_MEM_ADDR]);
|
|
if (!tb[IWL_TM_ATTR_BUFFER_SIZE]) {
|
|
IWL_ERR(tst->trans, "Error finding size for memory reading\n");
|
|
return -ENOMSG;
|
|
}
|
|
size = nla_get_u32(tb[IWL_TM_ATTR_BUFFER_SIZE]);
|
|
|
|
if (cmd == IWL_TM_CMD_APP2DEV_INDIRECT_BUFFER_READ) {
|
|
return iwl_test_indirect_read(tst, addr, size);
|
|
} else {
|
|
if (!tb[IWL_TM_ATTR_BUFFER_DUMP])
|
|
return -EINVAL;
|
|
buf = (unsigned char *)nla_data(tb[IWL_TM_ATTR_BUFFER_DUMP]);
|
|
return iwl_test_indirect_write(tst, addr, size, buf);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Enable notifications to user space
|
|
*/
|
|
static int iwl_test_notifications(struct iwl_test *tst,
|
|
struct nlattr **tb)
|
|
{
|
|
tst->notify = nla_get_flag(tb[IWL_TM_ATTR_ENABLE_NOTIFICATION]);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Handles the request to get the device id
|
|
*/
|
|
static int iwl_test_get_dev_id(struct iwl_test *tst, struct nlattr **tb)
|
|
{
|
|
u32 devid = tst->trans->hw_id;
|
|
struct sk_buff *skb;
|
|
int status;
|
|
|
|
IWL_DEBUG_INFO(tst->trans, "hw version: 0x%x\n", devid);
|
|
|
|
skb = iwl_test_alloc_reply(tst, 20);
|
|
if (!skb) {
|
|
IWL_ERR(tst->trans, "Memory allocation fail\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (nla_put_u32(skb, IWL_TM_ATTR_DEVICE_ID, devid))
|
|
goto nla_put_failure;
|
|
status = iwl_test_reply(tst, skb);
|
|
if (status < 0)
|
|
IWL_ERR(tst->trans, "Error sending msg : %d\n", status);
|
|
|
|
return 0;
|
|
|
|
nla_put_failure:
|
|
kfree_skb(skb);
|
|
return -EMSGSIZE;
|
|
}
|
|
|
|
/*
|
|
* Handles the request to get the FW version
|
|
*/
|
|
static int iwl_test_get_fw_ver(struct iwl_test *tst, struct nlattr **tb)
|
|
{
|
|
struct sk_buff *skb;
|
|
int status;
|
|
u32 ver = iwl_test_fw_ver(tst);
|
|
|
|
IWL_DEBUG_INFO(tst->trans, "uCode version raw: 0x%x\n", ver);
|
|
|
|
skb = iwl_test_alloc_reply(tst, 20);
|
|
if (!skb) {
|
|
IWL_ERR(tst->trans, "Memory allocation fail\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (nla_put_u32(skb, IWL_TM_ATTR_FW_VERSION, ver))
|
|
goto nla_put_failure;
|
|
|
|
status = iwl_test_reply(tst, skb);
|
|
if (status < 0)
|
|
IWL_ERR(tst->trans, "Error sending msg : %d\n", status);
|
|
|
|
return 0;
|
|
|
|
nla_put_failure:
|
|
kfree_skb(skb);
|
|
return -EMSGSIZE;
|
|
}
|
|
|
|
/*
|
|
* Parse the netlink message and validate that the IWL_TM_ATTR_CMD exists
|
|
*/
|
|
int iwl_test_parse(struct iwl_test *tst, struct nlattr **tb,
|
|
void *data, int len)
|
|
{
|
|
int result;
|
|
|
|
result = nla_parse(tb, IWL_TM_ATTR_MAX - 1, data, len,
|
|
iwl_testmode_gnl_msg_policy);
|
|
if (result) {
|
|
IWL_ERR(tst->trans, "Fail parse gnl msg: %d\n", result);
|
|
return result;
|
|
}
|
|
|
|
/* IWL_TM_ATTR_COMMAND is absolutely mandatory */
|
|
if (!tb[IWL_TM_ATTR_COMMAND]) {
|
|
IWL_ERR(tst->trans, "Missing testmode command type\n");
|
|
return -ENOMSG;
|
|
}
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iwl_test_parse);
|
|
|
|
/*
|
|
* Handle test commands.
|
|
* Returns 1 for unknown commands (not handled by the test object); negative
|
|
* value in case of error.
|
|
*/
|
|
int iwl_test_handle_cmd(struct iwl_test *tst, struct nlattr **tb)
|
|
{
|
|
int result;
|
|
|
|
switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
|
|
case IWL_TM_CMD_APP2DEV_UCODE:
|
|
IWL_DEBUG_INFO(tst->trans, "test cmd to uCode\n");
|
|
result = iwl_test_fw_cmd(tst, tb);
|
|
break;
|
|
|
|
case IWL_TM_CMD_APP2DEV_DIRECT_REG_READ32:
|
|
case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE32:
|
|
case IWL_TM_CMD_APP2DEV_DIRECT_REG_WRITE8:
|
|
IWL_DEBUG_INFO(tst->trans, "test cmd to register\n");
|
|
result = iwl_test_reg(tst, tb);
|
|
break;
|
|
|
|
case IWL_TM_CMD_APP2DEV_BEGIN_TRACE:
|
|
IWL_DEBUG_INFO(tst->trans, "test uCode trace cmd to driver\n");
|
|
result = iwl_test_trace_begin(tst, tb);
|
|
break;
|
|
|
|
case IWL_TM_CMD_APP2DEV_END_TRACE:
|
|
iwl_test_trace_stop(tst);
|
|
result = 0;
|
|
break;
|
|
|
|
case IWL_TM_CMD_APP2DEV_INDIRECT_BUFFER_READ:
|
|
case IWL_TM_CMD_APP2DEV_INDIRECT_BUFFER_WRITE:
|
|
IWL_DEBUG_INFO(tst->trans, "test indirect memory cmd\n");
|
|
result = iwl_test_indirect_mem(tst, tb);
|
|
break;
|
|
|
|
case IWL_TM_CMD_APP2DEV_NOTIFICATIONS:
|
|
IWL_DEBUG_INFO(tst->trans, "test notifications cmd\n");
|
|
result = iwl_test_notifications(tst, tb);
|
|
break;
|
|
|
|
case IWL_TM_CMD_APP2DEV_GET_FW_VERSION:
|
|
IWL_DEBUG_INFO(tst->trans, "test get FW ver cmd\n");
|
|
result = iwl_test_get_fw_ver(tst, tb);
|
|
break;
|
|
|
|
case IWL_TM_CMD_APP2DEV_GET_DEVICE_ID:
|
|
IWL_DEBUG_INFO(tst->trans, "test Get device ID cmd\n");
|
|
result = iwl_test_get_dev_id(tst, tb);
|
|
break;
|
|
|
|
default:
|
|
IWL_DEBUG_INFO(tst->trans, "Unknown test command\n");
|
|
result = 1;
|
|
break;
|
|
}
|
|
return result;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iwl_test_handle_cmd);
|
|
|
|
static int iwl_test_trace_dump(struct iwl_test *tst, struct sk_buff *skb,
|
|
struct netlink_callback *cb)
|
|
{
|
|
int idx, length;
|
|
|
|
if (!tst->trace.enabled || !tst->trace.trace_addr)
|
|
return -EFAULT;
|
|
|
|
idx = cb->args[4];
|
|
if (idx >= tst->trace.nchunks)
|
|
return -ENOENT;
|
|
|
|
length = DUMP_CHUNK_SIZE;
|
|
if (((idx + 1) == tst->trace.nchunks) &&
|
|
(tst->trace.size % DUMP_CHUNK_SIZE))
|
|
length = tst->trace.size %
|
|
DUMP_CHUNK_SIZE;
|
|
|
|
if (nla_put(skb, IWL_TM_ATTR_TRACE_DUMP, length,
|
|
tst->trace.trace_addr + (DUMP_CHUNK_SIZE * idx)))
|
|
goto nla_put_failure;
|
|
|
|
cb->args[4] = ++idx;
|
|
return 0;
|
|
|
|
nla_put_failure:
|
|
return -ENOBUFS;
|
|
}
|
|
|
|
static int iwl_test_buffer_dump(struct iwl_test *tst, struct sk_buff *skb,
|
|
struct netlink_callback *cb)
|
|
{
|
|
int idx, length;
|
|
|
|
if (!tst->mem.in_read)
|
|
return -EFAULT;
|
|
|
|
idx = cb->args[4];
|
|
if (idx >= tst->mem.nchunks) {
|
|
iwl_test_mem_stop(tst);
|
|
return -ENOENT;
|
|
}
|
|
|
|
length = DUMP_CHUNK_SIZE;
|
|
if (((idx + 1) == tst->mem.nchunks) &&
|
|
(tst->mem.size % DUMP_CHUNK_SIZE))
|
|
length = tst->mem.size % DUMP_CHUNK_SIZE;
|
|
|
|
if (nla_put(skb, IWL_TM_ATTR_BUFFER_DUMP, length,
|
|
tst->mem.addr + (DUMP_CHUNK_SIZE * idx)))
|
|
goto nla_put_failure;
|
|
|
|
cb->args[4] = ++idx;
|
|
return 0;
|
|
|
|
nla_put_failure:
|
|
return -ENOBUFS;
|
|
}
|
|
|
|
/*
|
|
* Handle dump commands.
|
|
* Returns 1 for unknown commands (not handled by the test object); negative
|
|
* value in case of error.
|
|
*/
|
|
int iwl_test_dump(struct iwl_test *tst, u32 cmd, struct sk_buff *skb,
|
|
struct netlink_callback *cb)
|
|
{
|
|
int result;
|
|
|
|
switch (cmd) {
|
|
case IWL_TM_CMD_APP2DEV_READ_TRACE:
|
|
IWL_DEBUG_INFO(tst->trans, "uCode trace cmd\n");
|
|
result = iwl_test_trace_dump(tst, skb, cb);
|
|
break;
|
|
|
|
case IWL_TM_CMD_APP2DEV_INDIRECT_BUFFER_DUMP:
|
|
IWL_DEBUG_INFO(tst->trans, "testmode sram dump cmd\n");
|
|
result = iwl_test_buffer_dump(tst, skb, cb);
|
|
break;
|
|
|
|
default:
|
|
result = 1;
|
|
break;
|
|
}
|
|
return result;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iwl_test_dump);
|
|
|
|
/*
|
|
* Multicast a spontaneous messages from the device to the user space.
|
|
*/
|
|
static void iwl_test_send_rx(struct iwl_test *tst,
|
|
struct iwl_rx_cmd_buffer *rxb)
|
|
{
|
|
struct sk_buff *skb;
|
|
struct iwl_rx_packet *data;
|
|
int length;
|
|
|
|
data = rxb_addr(rxb);
|
|
length = le32_to_cpu(data->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
|
|
|
|
/* the length doesn't include len_n_flags field, so add it manually */
|
|
length += sizeof(__le32);
|
|
|
|
skb = iwl_test_alloc_event(tst, length + 20);
|
|
if (skb == NULL) {
|
|
IWL_ERR(tst->trans, "Out of memory for message to user\n");
|
|
return;
|
|
}
|
|
|
|
if (nla_put_u32(skb, IWL_TM_ATTR_COMMAND,
|
|
IWL_TM_CMD_DEV2APP_UCODE_RX_PKT) ||
|
|
nla_put(skb, IWL_TM_ATTR_UCODE_RX_PKT, length, data))
|
|
goto nla_put_failure;
|
|
|
|
iwl_test_event(tst, skb);
|
|
return;
|
|
|
|
nla_put_failure:
|
|
kfree_skb(skb);
|
|
IWL_ERR(tst->trans, "Ouch, overran buffer, check allocation!\n");
|
|
}
|
|
|
|
/*
|
|
* Called whenever a Rx frames is recevied from the device. If notifications to
|
|
* the user space are requested, sends the frames to the user.
|
|
*/
|
|
void iwl_test_rx(struct iwl_test *tst, struct iwl_rx_cmd_buffer *rxb)
|
|
{
|
|
if (tst->notify)
|
|
iwl_test_send_rx(tst, rxb);
|
|
}
|
|
EXPORT_SYMBOL_GPL(iwl_test_rx);
|