294 lines
11 KiB
C
294 lines
11 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This contains hardware definitions that are common between i.MX21 and
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* i.MX27.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __MACH_MX2x_H__
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#define __MACH_MX2x_H__
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/* The following addresses are common between i.MX21 and i.MX27 */
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/* Register offsets */
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#define MX2x_AIPI_BASE_ADDR 0x10000000
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#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
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#define MX2x_AIPI_SIZE SZ_1M
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#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
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#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
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#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
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#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
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#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
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#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
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#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
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#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
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#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
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#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
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#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
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#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
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#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
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#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
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#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
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#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
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#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
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#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
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#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
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#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
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#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
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#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
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#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
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#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
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#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
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#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
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#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
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#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
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#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
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#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
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#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
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#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
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#define MX2x_AVIC_BASE_ADDR 0x10040000
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#define MX2x_SAHB1_BASE_ADDR 0x80000000
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#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
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#define MX2x_SAHB1_SIZE SZ_1M
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#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
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/*
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* This macro defines the physical to virtual address mapping for all the
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* peripheral modules. It is used by passing in the physical address as x
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* and returning the virtual address. If the physical address is not mapped,
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* it returns 0xDEADBEEF
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*/
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#define IO_ADDRESS(x) \
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(void __force __iomem *) \
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(((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
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AIPI_IO_ADDRESS(x) : \
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((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
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SAHB1_IO_ADDRESS(x) : \
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((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
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X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
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/* define the address mapping macros: in physical address order */
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#define AIPI_IO_ADDRESS(x) \
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(((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
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#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
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#define SAHB1_IO_ADDRESS(x) \
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(((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
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#define CS4_IO_ADDRESS(x) \
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(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
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#define X_MEMC_IO_ADDRESS(x) \
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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#define PCMCIA_IO_ADDRESS(x) \
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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/* fixed interrupt numbers */
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#define MX2x_INT_CSPI3 6
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#define MX2x_INT_GPIO 8
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#define MX2x_INT_SDHC2 10
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#define MX2x_INT_SDHC1 11
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#define MX2x_INT_I2C 12
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#define MX2x_INT_SSI2 13
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#define MX2x_INT_SSI1 14
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#define MX2x_INT_CSPI2 15
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#define MX2x_INT_CSPI1 16
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#define MX2x_INT_UART4 17
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#define MX2x_INT_UART3 18
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#define MX2x_INT_UART2 19
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#define MX2x_INT_UART1 20
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#define MX2x_INT_KPP 21
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#define MX2x_INT_RTC 22
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#define MX2x_INT_PWM 23
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#define MX2x_INT_GPT3 24
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#define MX2x_INT_GPT2 25
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#define MX2x_INT_GPT1 26
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#define MX2x_INT_WDOG 27
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#define MX2x_INT_PCMCIA 28
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#define MX2x_INT_NANDFC 29
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#define MX2x_INT_CSI 31
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#define MX2x_INT_DMACH0 32
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#define MX2x_INT_DMACH1 33
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#define MX2x_INT_DMACH2 34
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#define MX2x_INT_DMACH3 35
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#define MX2x_INT_DMACH4 36
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#define MX2x_INT_DMACH5 37
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#define MX2x_INT_DMACH6 38
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#define MX2x_INT_DMACH7 39
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#define MX2x_INT_DMACH8 40
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#define MX2x_INT_DMACH9 41
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#define MX2x_INT_DMACH10 42
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#define MX2x_INT_DMACH11 43
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#define MX2x_INT_DMACH12 44
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#define MX2x_INT_DMACH13 45
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#define MX2x_INT_DMACH14 46
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#define MX2x_INT_DMACH15 47
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#define MX2x_INT_EMMAPRP 51
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#define MX2x_INT_EMMAPP 52
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#define MX2x_INT_SLCDC 60
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#define MX2x_INT_LCDC 61
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/* fixed DMA request numbers */
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#define MX2x_DMA_REQ_CSPI3_RX 1
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#define MX2x_DMA_REQ_CSPI3_TX 2
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#define MX2x_DMA_REQ_EXT 3
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#define MX2x_DMA_REQ_SDHC2 6
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#define MX2x_DMA_REQ_SDHC1 7
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#define MX2x_DMA_REQ_SSI2_RX0 8
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#define MX2x_DMA_REQ_SSI2_TX0 9
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#define MX2x_DMA_REQ_SSI2_RX1 10
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#define MX2x_DMA_REQ_SSI2_TX1 11
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#define MX2x_DMA_REQ_SSI1_RX0 12
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#define MX2x_DMA_REQ_SSI1_TX0 13
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#define MX2x_DMA_REQ_SSI1_RX1 14
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#define MX2x_DMA_REQ_SSI1_TX1 15
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#define MX2x_DMA_REQ_CSPI2_RX 16
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#define MX2x_DMA_REQ_CSPI2_TX 17
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#define MX2x_DMA_REQ_CSPI1_RX 18
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#define MX2x_DMA_REQ_CSPI1_TX 19
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#define MX2x_DMA_REQ_UART4_RX 20
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#define MX2x_DMA_REQ_UART4_TX 21
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#define MX2x_DMA_REQ_UART3_RX 22
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#define MX2x_DMA_REQ_UART3_TX 23
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#define MX2x_DMA_REQ_UART2_RX 24
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#define MX2x_DMA_REQ_UART2_TX 25
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#define MX2x_DMA_REQ_UART1_RX 26
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#define MX2x_DMA_REQ_UART1_TX 27
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#define MX2x_DMA_REQ_CSI_STAT 30
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#define MX2x_DMA_REQ_CSI_RX 31
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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/* these should go away */
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#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
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#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
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#define AIPI_SIZE MX2x_AIPI_SIZE
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#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
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#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
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#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
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#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
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#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
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#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
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#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
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#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
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#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
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#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
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#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
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#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
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#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
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#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
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#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
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#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
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#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
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#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
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#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
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#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
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#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
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#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
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#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
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#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
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#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
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#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
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#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
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#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
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#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
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#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
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#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
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#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
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#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
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#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
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#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
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#define SAHB1_SIZE MX2x_SAHB1_SIZE
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#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
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#define MXC_INT_CSPI3 MX2x_INT_CSPI3
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#define MXC_INT_GPIO MX2x_INT_GPIO
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#define MXC_INT_SDHC2 MX2x_INT_SDHC2
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#define MXC_INT_SDHC1 MX2x_INT_SDHC1
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#define MXC_INT_I2C MX2x_INT_I2C
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#define MXC_INT_SSI2 MX2x_INT_SSI2
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#define MXC_INT_SSI1 MX2x_INT_SSI1
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#define MXC_INT_CSPI2 MX2x_INT_CSPI2
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#define MXC_INT_CSPI1 MX2x_INT_CSPI1
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#define MXC_INT_UART4 MX2x_INT_UART4
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#define MXC_INT_UART3 MX2x_INT_UART3
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#define MXC_INT_UART2 MX2x_INT_UART2
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#define MXC_INT_UART1 MX2x_INT_UART1
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#define MXC_INT_KPP MX2x_INT_KPP
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#define MXC_INT_RTC MX2x_INT_RTC
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#define MXC_INT_PWM MX2x_INT_PWM
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#define MXC_INT_GPT3 MX2x_INT_GPT3
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#define MXC_INT_GPT2 MX2x_INT_GPT2
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#define MXC_INT_GPT1 MX2x_INT_GPT1
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#define MXC_INT_WDOG MX2x_INT_WDOG
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#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
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#define MXC_INT_NANDFC MX2x_INT_NANDFC
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#define MXC_INT_CSI MX2x_INT_CSI
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#define MXC_INT_DMACH0 MX2x_INT_DMACH0
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#define MXC_INT_DMACH1 MX2x_INT_DMACH1
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#define MXC_INT_DMACH2 MX2x_INT_DMACH2
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#define MXC_INT_DMACH3 MX2x_INT_DMACH3
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#define MXC_INT_DMACH4 MX2x_INT_DMACH4
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#define MXC_INT_DMACH5 MX2x_INT_DMACH5
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#define MXC_INT_DMACH6 MX2x_INT_DMACH6
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#define MXC_INT_DMACH7 MX2x_INT_DMACH7
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#define MXC_INT_DMACH8 MX2x_INT_DMACH8
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#define MXC_INT_DMACH9 MX2x_INT_DMACH9
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#define MXC_INT_DMACH10 MX2x_INT_DMACH10
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#define MXC_INT_DMACH11 MX2x_INT_DMACH11
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#define MXC_INT_DMACH12 MX2x_INT_DMACH12
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#define MXC_INT_DMACH13 MX2x_INT_DMACH13
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#define MXC_INT_DMACH14 MX2x_INT_DMACH14
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#define MXC_INT_DMACH15 MX2x_INT_DMACH15
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#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
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#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
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#define MXC_INT_SLCDC MX2x_INT_SLCDC
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#define MXC_INT_LCDC MX2x_INT_LCDC
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#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
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#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
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#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
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#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
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#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
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#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
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#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
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#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
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#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
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#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
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#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
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#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
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#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
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#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
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#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
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#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
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#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
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#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
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#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
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#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
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#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
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#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
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#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
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#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
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#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
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#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
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#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
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#endif
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#endif /* ifndef __MACH_MX2x_H__ */
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