480 lines
14 KiB
C
480 lines
14 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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// Copyright(c) 2015-17 Intel Corporation.
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#ifndef __SOUNDWIRE_H
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#define __SOUNDWIRE_H
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struct sdw_bus;
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struct sdw_slave;
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/* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
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/* SDW Broadcast Device Number */
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#define SDW_BROADCAST_DEV_NUM 15
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/* SDW Enumeration Device Number */
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#define SDW_ENUM_DEV_NUM 0
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/* SDW Group Device Numbers */
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#define SDW_GROUP12_DEV_NUM 12
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#define SDW_GROUP13_DEV_NUM 13
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/* SDW Master Device Number, not supported yet */
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#define SDW_MASTER_DEV_NUM 14
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#define SDW_NUM_DEV_ID_REGISTERS 6
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#define SDW_MAX_DEVICES 11
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/**
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* enum sdw_slave_status - Slave status
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* @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
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* @SDW_SLAVE_ATTACHED: Slave is attached with bus.
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* @SDW_SLAVE_ALERT: Some alert condition on the Slave
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* @SDW_SLAVE_RESERVED: Reserved for future use
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*/
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enum sdw_slave_status {
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SDW_SLAVE_UNATTACHED = 0,
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SDW_SLAVE_ATTACHED = 1,
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SDW_SLAVE_ALERT = 2,
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SDW_SLAVE_RESERVED = 3,
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};
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/**
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* enum sdw_command_response - Command response as defined by SDW spec
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* @SDW_CMD_OK: cmd was successful
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* @SDW_CMD_IGNORED: cmd was ignored
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* @SDW_CMD_FAIL: cmd was NACKed
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* @SDW_CMD_TIMEOUT: cmd timedout
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* @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
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*
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* NOTE: The enum is different than actual Spec as response in the Spec is
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* combination of ACK/NAK bits
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*
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* SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
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*/
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enum sdw_command_response {
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SDW_CMD_OK = 0,
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SDW_CMD_IGNORED = 1,
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SDW_CMD_FAIL = 2,
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SDW_CMD_TIMEOUT = 3,
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SDW_CMD_FAIL_OTHER = 4,
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};
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/*
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* SDW properties, defined in MIPI DisCo spec v1.0
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*/
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enum sdw_clk_stop_reset_behave {
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SDW_CLK_STOP_KEEP_STATUS = 1,
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};
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/**
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* enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
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* read
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* @SDW_P15_READ_IGNORED: Read is ignored
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* @SDW_P15_CMD_OK: Command is ok
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*/
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enum sdw_p15_behave {
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SDW_P15_READ_IGNORED = 0,
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SDW_P15_CMD_OK = 1,
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};
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/**
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* enum sdw_dpn_type - Data port types
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* @SDW_DPN_FULL: Full Data Port is supported
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* @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
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* DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
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* are not implemented.
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* @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
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* DPN_SampleCtrl2, DPN_HCtrl are not implemented.
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*/
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enum sdw_dpn_type {
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SDW_DPN_FULL = 0,
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SDW_DPN_SIMPLE = 1,
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SDW_DPN_REDUCED = 2,
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};
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/**
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* enum sdw_clk_stop_mode - Clock Stop modes
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* @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
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* restart
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* @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
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* not capable of continuing operation seamlessly when the clock restarts
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*/
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enum sdw_clk_stop_mode {
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SDW_CLK_STOP_MODE0 = 0,
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SDW_CLK_STOP_MODE1 = 1,
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};
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/**
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* struct sdw_dp0_prop - DP0 properties
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* @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
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* (inclusive)
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* @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
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* (inclusive)
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* @num_words: number of wordlengths supported
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* @words: wordlengths supported
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* @flow_controlled: Slave implementation results in an OK_NotReady
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* response
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* @simple_ch_prep_sm: If channel prepare sequence is required
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* @device_interrupts: If implementation-defined interrupts are supported
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*
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* The wordlengths are specified by Spec as max, min AND number of
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* discrete values, implementation can define based on the wordlengths they
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* support
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*/
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struct sdw_dp0_prop {
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u32 max_word;
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u32 min_word;
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u32 num_words;
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u32 *words;
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bool flow_controlled;
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bool simple_ch_prep_sm;
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bool device_interrupts;
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};
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/**
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* struct sdw_dpn_audio_mode - Audio mode properties for DPn
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* @bus_min_freq: Minimum bus frequency, in Hz
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* @bus_max_freq: Maximum bus frequency, in Hz
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* @bus_num_freq: Number of discrete frequencies supported
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* @bus_freq: Discrete bus frequencies, in Hz
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* @min_freq: Minimum sampling frequency, in Hz
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* @max_freq: Maximum sampling bus frequency, in Hz
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* @num_freq: Number of discrete sampling frequency supported
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* @freq: Discrete sampling frequencies, in Hz
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* @prep_ch_behave: Specifies the dependencies between Channel Prepare
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* sequence and bus clock configuration
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* If 0, Channel Prepare can happen at any Bus clock rate
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* If 1, Channel Prepare sequence shall happen only after Bus clock is
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* changed to a frequency supported by this mode or compatible modes
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* described by the next field
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* @glitchless: Bitmap describing possible glitchless transitions from this
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* Audio Mode to other Audio Modes
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*/
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struct sdw_dpn_audio_mode {
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u32 bus_min_freq;
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u32 bus_max_freq;
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u32 bus_num_freq;
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u32 *bus_freq;
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u32 max_freq;
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u32 min_freq;
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u32 num_freq;
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u32 *freq;
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u32 prep_ch_behave;
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u32 glitchless;
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};
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/**
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* struct sdw_dpn_prop - Data Port DPn properties
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* @num: port number
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* @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
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* (inclusive)
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* @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
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* (inclusive)
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* @num_words: Number of discrete supported wordlengths
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* @words: Discrete supported wordlength
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* @type: Data port type. Full, Simplified or Reduced
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* @max_grouping: Maximum number of samples that can be grouped together for
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* a full data port
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* @simple_ch_prep_sm: If the port supports simplified channel prepare state
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* machine
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* @ch_prep_timeout: Port-specific timeout value, in milliseconds
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* @device_interrupts: If set, each bit corresponds to support for
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* implementation-defined interrupts
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* @max_ch: Maximum channels supported
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* @min_ch: Minimum channels supported
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* @num_ch: Number of discrete channels supported
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* @ch: Discrete channels supported
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* @num_ch_combinations: Number of channel combinations supported
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* @ch_combinations: Channel combinations supported
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* @modes: SDW mode supported
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* @max_async_buffer: Number of samples that this port can buffer in
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* asynchronous modes
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* @block_pack_mode: Type of block port mode supported
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* @port_encoding: Payload Channel Sample encoding schemes supported
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* @audio_modes: Audio modes supported
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*/
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struct sdw_dpn_prop {
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u32 num;
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u32 max_word;
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u32 min_word;
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u32 num_words;
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u32 *words;
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enum sdw_dpn_type type;
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u32 max_grouping;
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bool simple_ch_prep_sm;
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u32 ch_prep_timeout;
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u32 device_interrupts;
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u32 max_ch;
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u32 min_ch;
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u32 num_ch;
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u32 *ch;
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u32 num_ch_combinations;
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u32 *ch_combinations;
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u32 modes;
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u32 max_async_buffer;
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bool block_pack_mode;
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u32 port_encoding;
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struct sdw_dpn_audio_mode *audio_modes;
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};
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/**
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* struct sdw_slave_prop - SoundWire Slave properties
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* @mipi_revision: Spec version of the implementation
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* @wake_capable: Wake-up events are supported
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* @test_mode_capable: If test mode is supported
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* @clk_stop_mode1: Clock-Stop Mode 1 is supported
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* @simple_clk_stop_capable: Simple clock mode is supported
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* @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
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* Machine transitions, in milliseconds
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* @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
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* transitions, in milliseconds
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* @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
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* state machine (P=1 SCSP_SM) after exit from clock-stop mode1
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* @high_PHY_capable: Slave is HighPHY capable
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* @paging_support: Slave implements paging registers SCP_AddrPage1 and
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* SCP_AddrPage2
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* @bank_delay_support: Slave implements bank delay/bridge support registers
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* SCP_BankDelay and SCP_NextFrame
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* @p15_behave: Slave behavior when the Master attempts a read to the Port15
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* alias
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* @lane_control_support: Slave supports lane control
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* @master_count: Number of Masters present on this Slave
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* @source_ports: Bitmap identifying source ports
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* @sink_ports: Bitmap identifying sink ports
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* @dp0_prop: Data Port 0 properties
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* @src_dpn_prop: Source Data Port N properties
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* @sink_dpn_prop: Sink Data Port N properties
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*/
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struct sdw_slave_prop {
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u32 mipi_revision;
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bool wake_capable;
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bool test_mode_capable;
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bool clk_stop_mode1;
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bool simple_clk_stop_capable;
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u32 clk_stop_timeout;
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u32 ch_prep_timeout;
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enum sdw_clk_stop_reset_behave reset_behave;
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bool high_PHY_capable;
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bool paging_support;
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bool bank_delay_support;
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enum sdw_p15_behave p15_behave;
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bool lane_control_support;
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u32 master_count;
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u32 source_ports;
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u32 sink_ports;
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struct sdw_dp0_prop *dp0_prop;
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struct sdw_dpn_prop *src_dpn_prop;
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struct sdw_dpn_prop *sink_dpn_prop;
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};
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/**
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* struct sdw_master_prop - Master properties
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* @revision: MIPI spec version of the implementation
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* @master_count: Number of masters
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* @clk_stop_mode: Bitmap for Clock Stop modes supported
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* @max_freq: Maximum Bus clock frequency, in Hz
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* @num_clk_gears: Number of clock gears supported
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* @clk_gears: Clock gears supported
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* @num_freq: Number of clock frequencies supported, in Hz
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* @freq: Clock frequencies supported, in Hz
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* @default_frame_rate: Controller default Frame rate, in Hz
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* @default_row: Number of rows
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* @default_col: Number of columns
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* @dynamic_frame: Dynamic frame supported
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* @err_threshold: Number of times that software may retry sending a single
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* command
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* @dpn_prop: Data Port N properties
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*/
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struct sdw_master_prop {
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u32 revision;
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u32 master_count;
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enum sdw_clk_stop_mode clk_stop_mode;
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u32 max_freq;
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u32 num_clk_gears;
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u32 *clk_gears;
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u32 num_freq;
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u32 *freq;
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u32 default_frame_rate;
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u32 default_row;
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u32 default_col;
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bool dynamic_frame;
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u32 err_threshold;
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struct sdw_dpn_prop *dpn_prop;
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};
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int sdw_master_read_prop(struct sdw_bus *bus);
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int sdw_slave_read_prop(struct sdw_slave *slave);
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/*
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* SDW Slave Structures and APIs
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*/
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/**
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* struct sdw_slave_id - Slave ID
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* @mfg_id: MIPI Manufacturer ID
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* @part_id: Device Part ID
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* @class_id: MIPI Class ID, unused now.
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* Currently a placeholder in MIPI SoundWire Spec
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* @unique_id: Device unique ID
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* @sdw_version: SDW version implemented
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*
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* The order of the IDs here does not follow the DisCo spec definitions
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*/
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struct sdw_slave_id {
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__u16 mfg_id;
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__u16 part_id;
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__u8 class_id;
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__u8 unique_id:4;
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__u8 sdw_version:4;
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};
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/**
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* struct sdw_slave_intr_status - Slave interrupt status
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* @control_port: control port status
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* @port: data port status
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*/
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struct sdw_slave_intr_status {
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u8 control_port;
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u8 port[15];
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};
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/**
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* struct sdw_slave_ops - Slave driver callback ops
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* @read_prop: Read Slave properties
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* @interrupt_callback: Device interrupt notification (invoked in thread
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* context)
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* @update_status: Update Slave status
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*/
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struct sdw_slave_ops {
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int (*read_prop)(struct sdw_slave *sdw);
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int (*interrupt_callback)(struct sdw_slave *slave,
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struct sdw_slave_intr_status *status);
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int (*update_status)(struct sdw_slave *slave,
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enum sdw_slave_status status);
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};
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/**
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* struct sdw_slave - SoundWire Slave
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* @id: MIPI device ID
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* @dev: Linux device
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* @status: Status reported by the Slave
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* @bus: Bus handle
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* @ops: Slave callback ops
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* @prop: Slave properties
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* @node: node for bus list
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* @port_ready: Port ready completion flag for each Slave port
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* @dev_num: Device Number assigned by Bus
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*/
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struct sdw_slave {
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struct sdw_slave_id id;
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struct device dev;
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enum sdw_slave_status status;
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struct sdw_bus *bus;
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const struct sdw_slave_ops *ops;
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struct sdw_slave_prop prop;
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struct list_head node;
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struct completion *port_ready;
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u16 dev_num;
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};
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#define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
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struct sdw_driver {
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const char *name;
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int (*probe)(struct sdw_slave *sdw,
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const struct sdw_device_id *id);
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int (*remove)(struct sdw_slave *sdw);
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void (*shutdown)(struct sdw_slave *sdw);
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const struct sdw_device_id *id_table;
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const struct sdw_slave_ops *ops;
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struct device_driver driver;
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};
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#define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
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{ .mfg_id = (_mfg_id), .part_id = (_part_id), \
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.driver_data = (unsigned long)(_drv_data) }
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int sdw_handle_slave_status(struct sdw_bus *bus,
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enum sdw_slave_status status[]);
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/*
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* SDW master structures and APIs
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*/
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struct sdw_msg;
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/**
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* struct sdw_defer - SDW deffered message
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* @length: message length
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* @complete: message completion
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* @msg: SDW message
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*/
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struct sdw_defer {
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int length;
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struct completion complete;
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struct sdw_msg *msg;
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};
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/**
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* struct sdw_master_ops - Master driver ops
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* @read_prop: Read Master properties
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* @xfer_msg: Transfer message callback
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* @xfer_msg_defer: Defer version of transfer message callback
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* @reset_page_addr: Reset the SCP page address registers
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*/
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struct sdw_master_ops {
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int (*read_prop)(struct sdw_bus *bus);
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enum sdw_command_response (*xfer_msg)
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(struct sdw_bus *bus, struct sdw_msg *msg);
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enum sdw_command_response (*xfer_msg_defer)
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(struct sdw_bus *bus, struct sdw_msg *msg,
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struct sdw_defer *defer);
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enum sdw_command_response (*reset_page_addr)
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(struct sdw_bus *bus, unsigned int dev_num);
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};
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/**
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* struct sdw_bus - SoundWire bus
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* @dev: Master linux device
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* @link_id: Link id number, can be 0 to N, unique for each Master
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* @slaves: list of Slaves on this bus
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* @assigned: Bitmap for Slave device numbers.
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* Bit set implies used number, bit clear implies unused number.
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* @bus_lock: bus lock
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* @msg_lock: message lock
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* @ops: Master callback ops
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* @prop: Master properties
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* @defer_msg: Defer message
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* @clk_stop_timeout: Clock stop timeout computed
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*/
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struct sdw_bus {
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struct device *dev;
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unsigned int link_id;
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struct list_head slaves;
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DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
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struct mutex bus_lock;
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struct mutex msg_lock;
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const struct sdw_master_ops *ops;
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struct sdw_master_prop prop;
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struct sdw_defer defer_msg;
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unsigned int clk_stop_timeout;
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};
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int sdw_add_bus_master(struct sdw_bus *bus);
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void sdw_delete_bus_master(struct sdw_bus *bus);
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/* messaging and data APIs */
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int sdw_read(struct sdw_slave *slave, u32 addr);
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int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
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int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
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int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
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#endif /* __SOUNDWIRE_H */
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