827 lines
21 KiB
C
827 lines
21 KiB
C
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Xudong Chen <xudong.chen@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#define I2C_RS_TRANSFER (1 << 4)
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#define I2C_HS_NACKERR (1 << 2)
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#define I2C_ACKERR (1 << 1)
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#define I2C_TRANSAC_COMP (1 << 0)
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#define I2C_TRANSAC_START (1 << 0)
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#define I2C_RS_MUL_CNFG (1 << 15)
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#define I2C_RS_MUL_TRIG (1 << 14)
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#define I2C_DCM_DISABLE 0x0000
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#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
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#define I2C_IO_CONFIG_PUSH_PULL 0x0000
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#define I2C_SOFT_RST 0x0001
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#define I2C_FIFO_ADDR_CLR 0x0001
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#define I2C_DELAY_LEN 0x0002
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#define I2C_ST_START_CON 0x8001
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#define I2C_FS_START_CON 0x1800
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#define I2C_TIME_CLR_VALUE 0x0000
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#define I2C_TIME_DEFAULT_VALUE 0x0003
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#define I2C_FS_TIME_INIT_VALUE 0x1303
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#define I2C_WRRD_TRANAC_VALUE 0x0002
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#define I2C_RD_TRANAC_VALUE 0x0001
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#define I2C_DMA_CON_TX 0x0000
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#define I2C_DMA_CON_RX 0x0001
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#define I2C_DMA_START_EN 0x0001
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#define I2C_DMA_INT_FLAG_NONE 0x0000
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#define I2C_DMA_CLR_FLAG 0x0000
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#define I2C_DMA_HARD_RST 0x0002
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#define I2C_DMA_4G_MODE 0x0001
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#define I2C_DEFAULT_SPEED 100000 /* hz */
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#define MAX_FS_MODE_SPEED 400000
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#define MAX_HS_MODE_SPEED 3400000
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#define MAX_SAMPLE_CNT_DIV 8
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#define MAX_STEP_CNT_DIV 64
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#define MAX_HS_STEP_CNT_DIV 8
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#define I2C_CONTROL_RS (0x1 << 1)
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#define I2C_CONTROL_DMA_EN (0x1 << 2)
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#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
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#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
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#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
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#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
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#define I2C_CONTROL_WRAPPER (0x1 << 0)
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#define I2C_DRV_NAME "i2c-mt65xx"
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enum DMA_REGS_OFFSET {
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OFFSET_INT_FLAG = 0x0,
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OFFSET_INT_EN = 0x04,
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OFFSET_EN = 0x08,
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OFFSET_RST = 0x0c,
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OFFSET_CON = 0x18,
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OFFSET_TX_MEM_ADDR = 0x1c,
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OFFSET_RX_MEM_ADDR = 0x20,
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OFFSET_TX_LEN = 0x24,
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OFFSET_RX_LEN = 0x28,
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OFFSET_TX_4G_MODE = 0x54,
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OFFSET_RX_4G_MODE = 0x58,
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};
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enum i2c_trans_st_rs {
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I2C_TRANS_STOP = 0,
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I2C_TRANS_REPEATED_START,
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};
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enum mtk_trans_op {
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I2C_MASTER_WR = 1,
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I2C_MASTER_RD,
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I2C_MASTER_WRRD,
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};
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enum I2C_REGS_OFFSET {
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OFFSET_DATA_PORT = 0x0,
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OFFSET_SLAVE_ADDR = 0x04,
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OFFSET_INTR_MASK = 0x08,
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OFFSET_INTR_STAT = 0x0c,
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OFFSET_CONTROL = 0x10,
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OFFSET_TRANSFER_LEN = 0x14,
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OFFSET_TRANSAC_LEN = 0x18,
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OFFSET_DELAY_LEN = 0x1c,
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OFFSET_TIMING = 0x20,
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OFFSET_START = 0x24,
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OFFSET_EXT_CONF = 0x28,
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OFFSET_FIFO_STAT = 0x30,
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OFFSET_FIFO_THRESH = 0x34,
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OFFSET_FIFO_ADDR_CLR = 0x38,
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OFFSET_IO_CONFIG = 0x40,
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OFFSET_RSV_DEBUG = 0x44,
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OFFSET_HS = 0x48,
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OFFSET_SOFTRESET = 0x50,
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OFFSET_DCM_EN = 0x54,
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OFFSET_PATH_DIR = 0x60,
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OFFSET_DEBUGSTAT = 0x64,
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OFFSET_DEBUGCTRL = 0x68,
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OFFSET_TRANSFER_LEN_AUX = 0x6c,
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};
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struct mtk_i2c_compatible {
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const struct i2c_adapter_quirks *quirks;
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unsigned char pmic_i2c: 1;
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unsigned char dcm: 1;
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unsigned char auto_restart: 1;
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unsigned char aux_len_reg: 1;
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unsigned char support_33bits: 1;
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};
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struct mtk_i2c {
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struct i2c_adapter adap; /* i2c host adapter */
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struct device *dev;
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struct completion msg_complete;
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/* set in i2c probe */
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void __iomem *base; /* i2c base addr */
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void __iomem *pdmabase; /* dma base address*/
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struct clk *clk_main; /* main clock for i2c bus */
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struct clk *clk_dma; /* DMA clock for i2c via DMA */
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struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
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bool have_pmic; /* can use i2c pins from PMIC */
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bool use_push_pull; /* IO config push-pull mode */
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u16 irq_stat; /* interrupt status */
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unsigned int speed_hz; /* The speed in transfer */
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enum mtk_trans_op op;
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u16 timing_reg;
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u16 high_speed_reg;
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unsigned char auto_restart;
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bool ignore_restart_irq;
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const struct mtk_i2c_compatible *dev_comp;
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};
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static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
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.flags = I2C_AQ_COMB_WRITE_THEN_READ,
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.max_num_msgs = 1,
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.max_write_len = 255,
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.max_read_len = 255,
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.max_comb_1st_msg_len = 255,
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.max_comb_2nd_msg_len = 31,
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};
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static const struct mtk_i2c_compatible mt6577_compat = {
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.quirks = &mt6577_i2c_quirks,
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.pmic_i2c = 0,
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.dcm = 1,
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.auto_restart = 0,
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.aux_len_reg = 0,
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.support_33bits = 0,
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};
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static const struct mtk_i2c_compatible mt6589_compat = {
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.quirks = &mt6577_i2c_quirks,
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.pmic_i2c = 1,
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.dcm = 0,
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.auto_restart = 0,
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.aux_len_reg = 0,
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.support_33bits = 0,
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};
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static const struct mtk_i2c_compatible mt8173_compat = {
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.pmic_i2c = 0,
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.dcm = 1,
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.auto_restart = 1,
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.aux_len_reg = 1,
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.support_33bits = 1,
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};
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static const struct of_device_id mtk_i2c_of_match[] = {
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{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
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{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
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{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
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{}
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};
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MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
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static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
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{
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int ret;
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ret = clk_prepare_enable(i2c->clk_dma);
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if (ret)
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return ret;
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ret = clk_prepare_enable(i2c->clk_main);
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if (ret)
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goto err_main;
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if (i2c->have_pmic) {
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ret = clk_prepare_enable(i2c->clk_pmic);
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if (ret)
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goto err_pmic;
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}
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return 0;
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err_pmic:
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clk_disable_unprepare(i2c->clk_main);
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err_main:
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clk_disable_unprepare(i2c->clk_dma);
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return ret;
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}
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static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
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{
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if (i2c->have_pmic)
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clk_disable_unprepare(i2c->clk_pmic);
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clk_disable_unprepare(i2c->clk_main);
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clk_disable_unprepare(i2c->clk_dma);
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}
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static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
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{
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u16 control_reg;
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writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
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/* Set ioconfig */
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if (i2c->use_push_pull)
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writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
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else
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writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
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if (i2c->dev_comp->dcm)
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writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
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writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
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writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
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/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
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if (i2c->have_pmic)
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writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
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control_reg = I2C_CONTROL_ACKERR_DET_EN |
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I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
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writew(control_reg, i2c->base + OFFSET_CONTROL);
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writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
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writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
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udelay(50);
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writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
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}
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/*
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* Calculate i2c port speed
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*
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* Hardware design:
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* i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
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* clock_div: fixed in hardware, but may be various in different SoCs
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*
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* The calculation want to pick the highest bus frequency that is still
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* less than or equal to i2c->speed_hz. The calculation try to get
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* sample_cnt and step_cn
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*/
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static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
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unsigned int clock_div)
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{
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unsigned int clk_src;
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unsigned int step_cnt;
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unsigned int sample_cnt;
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unsigned int max_step_cnt;
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unsigned int target_speed;
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unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
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unsigned int base_step_cnt;
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unsigned int opt_div;
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unsigned int best_mul;
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unsigned int cnt_mul;
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clk_src = parent_clk / clock_div;
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target_speed = i2c->speed_hz;
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if (target_speed > MAX_HS_MODE_SPEED)
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target_speed = MAX_HS_MODE_SPEED;
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if (target_speed > MAX_FS_MODE_SPEED)
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max_step_cnt = MAX_HS_STEP_CNT_DIV;
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else
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max_step_cnt = MAX_STEP_CNT_DIV;
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base_step_cnt = max_step_cnt;
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/* Find the best combination */
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opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
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best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
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/* Search for the best pair (sample_cnt, step_cnt) with
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* 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
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* 0 < step_cnt < max_step_cnt
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* sample_cnt * step_cnt >= opt_div
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* optimizing for sample_cnt * step_cnt being minimal
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*/
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for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
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step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
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cnt_mul = step_cnt * sample_cnt;
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if (step_cnt > max_step_cnt)
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continue;
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if (cnt_mul < best_mul) {
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best_mul = cnt_mul;
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base_sample_cnt = sample_cnt;
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base_step_cnt = step_cnt;
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if (best_mul == opt_div)
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break;
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}
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}
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sample_cnt = base_sample_cnt;
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step_cnt = base_step_cnt;
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if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
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/* In this case, hardware can't support such
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* low i2c_bus_freq
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*/
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dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
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return -EINVAL;
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}
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step_cnt--;
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sample_cnt--;
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if (target_speed > MAX_FS_MODE_SPEED) {
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/* Set the high speed mode register */
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i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
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i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
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(sample_cnt << 12) | (step_cnt << 8);
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} else {
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i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0);
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/* Disable the high speed transaction */
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i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
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}
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return 0;
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}
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static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
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{
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return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
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}
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static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
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int num, int left_num)
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{
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u16 addr_reg;
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u16 start_reg;
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u16 control_reg;
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u16 restart_flag = 0;
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u32 reg_4g_mode;
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dma_addr_t rpaddr = 0;
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dma_addr_t wpaddr = 0;
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int ret;
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i2c->irq_stat = 0;
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if (i2c->auto_restart)
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restart_flag = I2C_RS_TRANSFER;
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reinit_completion(&i2c->msg_complete);
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control_reg = readw(i2c->base + OFFSET_CONTROL) &
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~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
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if ((i2c->speed_hz > 400000) || (left_num >= 1))
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control_reg |= I2C_CONTROL_RS;
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if (i2c->op == I2C_MASTER_WRRD)
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control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
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writew(control_reg, i2c->base + OFFSET_CONTROL);
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/* set start condition */
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if (i2c->speed_hz <= 100000)
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writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
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else
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writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
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addr_reg = i2c_8bit_addr_from_msg(msgs);
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writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
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/* Clear interrupt status */
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writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
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writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
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/* Enable interrupt */
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writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
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/* Set transfer and transaction len */
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if (i2c->op == I2C_MASTER_WRRD) {
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if (i2c->dev_comp->aux_len_reg) {
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writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
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writew((msgs + 1)->len, i2c->base +
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OFFSET_TRANSFER_LEN_AUX);
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} else {
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writew(msgs->len | ((msgs + 1)->len) << 8,
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i2c->base + OFFSET_TRANSFER_LEN);
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}
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writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
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} else {
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writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
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writew(num, i2c->base + OFFSET_TRANSAC_LEN);
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}
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/* Prepare buffer data to start transfer */
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if (i2c->op == I2C_MASTER_RD) {
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writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
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writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
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rpaddr = dma_map_single(i2c->dev, msgs->buf,
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msgs->len, DMA_FROM_DEVICE);
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if (dma_mapping_error(i2c->dev, rpaddr))
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return -ENOMEM;
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if (i2c->dev_comp->support_33bits) {
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reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
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writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
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}
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writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
|
|
writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
|
|
} else if (i2c->op == I2C_MASTER_WR) {
|
|
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
|
|
writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
|
|
wpaddr = dma_map_single(i2c->dev, msgs->buf,
|
|
msgs->len, DMA_TO_DEVICE);
|
|
if (dma_mapping_error(i2c->dev, wpaddr))
|
|
return -ENOMEM;
|
|
|
|
if (i2c->dev_comp->support_33bits) {
|
|
reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
|
|
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
|
|
}
|
|
|
|
writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
|
|
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
|
|
} else {
|
|
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
|
|
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
|
|
wpaddr = dma_map_single(i2c->dev, msgs->buf,
|
|
msgs->len, DMA_TO_DEVICE);
|
|
if (dma_mapping_error(i2c->dev, wpaddr))
|
|
return -ENOMEM;
|
|
rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf,
|
|
(msgs + 1)->len,
|
|
DMA_FROM_DEVICE);
|
|
if (dma_mapping_error(i2c->dev, rpaddr)) {
|
|
dma_unmap_single(i2c->dev, wpaddr,
|
|
msgs->len, DMA_TO_DEVICE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (i2c->dev_comp->support_33bits) {
|
|
reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
|
|
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
|
|
|
|
reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
|
|
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
|
|
}
|
|
|
|
writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
|
|
writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
|
|
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
|
|
writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
|
|
}
|
|
|
|
writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
|
|
|
|
if (!i2c->auto_restart) {
|
|
start_reg = I2C_TRANSAC_START;
|
|
} else {
|
|
start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
|
|
if (left_num >= 1)
|
|
start_reg |= I2C_RS_MUL_CNFG;
|
|
}
|
|
writew(start_reg, i2c->base + OFFSET_START);
|
|
|
|
ret = wait_for_completion_timeout(&i2c->msg_complete,
|
|
i2c->adap.timeout);
|
|
|
|
/* Clear interrupt mask */
|
|
writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
|
|
I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
|
|
|
|
if (i2c->op == I2C_MASTER_WR) {
|
|
dma_unmap_single(i2c->dev, wpaddr,
|
|
msgs->len, DMA_TO_DEVICE);
|
|
} else if (i2c->op == I2C_MASTER_RD) {
|
|
dma_unmap_single(i2c->dev, rpaddr,
|
|
msgs->len, DMA_FROM_DEVICE);
|
|
} else {
|
|
dma_unmap_single(i2c->dev, wpaddr, msgs->len,
|
|
DMA_TO_DEVICE);
|
|
dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
|
|
DMA_FROM_DEVICE);
|
|
}
|
|
|
|
if (ret == 0) {
|
|
dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
|
|
mtk_i2c_init_hw(i2c);
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
completion_done(&i2c->msg_complete);
|
|
|
|
if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
|
|
dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
|
|
mtk_i2c_init_hw(i2c);
|
|
return -ENXIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_i2c_transfer(struct i2c_adapter *adap,
|
|
struct i2c_msg msgs[], int num)
|
|
{
|
|
int ret;
|
|
int left_num = num;
|
|
struct mtk_i2c *i2c = i2c_get_adapdata(adap);
|
|
|
|
ret = mtk_i2c_clock_enable(i2c);
|
|
if (ret)
|
|
return ret;
|
|
|
|
i2c->auto_restart = i2c->dev_comp->auto_restart;
|
|
|
|
/* checking if we can skip restart and optimize using WRRD mode */
|
|
if (i2c->auto_restart && num == 2) {
|
|
if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
|
|
msgs[0].addr == msgs[1].addr) {
|
|
i2c->auto_restart = 0;
|
|
}
|
|
}
|
|
|
|
if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
|
|
/* ignore the first restart irq after the master code,
|
|
* otherwise the first transfer will be discarded.
|
|
*/
|
|
i2c->ignore_restart_irq = true;
|
|
else
|
|
i2c->ignore_restart_irq = false;
|
|
|
|
while (left_num--) {
|
|
if (!msgs->buf) {
|
|
dev_dbg(i2c->dev, "data buffer is NULL.\n");
|
|
ret = -EINVAL;
|
|
goto err_exit;
|
|
}
|
|
|
|
if (msgs->flags & I2C_M_RD)
|
|
i2c->op = I2C_MASTER_RD;
|
|
else
|
|
i2c->op = I2C_MASTER_WR;
|
|
|
|
if (!i2c->auto_restart) {
|
|
if (num > 1) {
|
|
/* combined two messages into one transaction */
|
|
i2c->op = I2C_MASTER_WRRD;
|
|
left_num--;
|
|
}
|
|
}
|
|
|
|
/* always use DMA mode. */
|
|
ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
|
|
if (ret < 0)
|
|
goto err_exit;
|
|
|
|
msgs++;
|
|
}
|
|
/* the return value is number of executed messages */
|
|
ret = num;
|
|
|
|
err_exit:
|
|
mtk_i2c_clock_disable(i2c);
|
|
return ret;
|
|
}
|
|
|
|
static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
|
|
{
|
|
struct mtk_i2c *i2c = dev_id;
|
|
u16 restart_flag = 0;
|
|
u16 intr_stat;
|
|
|
|
if (i2c->auto_restart)
|
|
restart_flag = I2C_RS_TRANSFER;
|
|
|
|
intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
|
|
writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
|
|
|
|
/*
|
|
* when occurs ack error, i2c controller generate two interrupts
|
|
* first is the ack error interrupt, then the complete interrupt
|
|
* i2c->irq_stat need keep the two interrupt value.
|
|
*/
|
|
i2c->irq_stat |= intr_stat;
|
|
|
|
if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
|
|
i2c->ignore_restart_irq = false;
|
|
i2c->irq_stat = 0;
|
|
writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START,
|
|
i2c->base + OFFSET_START);
|
|
} else {
|
|
if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
|
|
complete(&i2c->msg_complete);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
}
|
|
|
|
static const struct i2c_algorithm mtk_i2c_algorithm = {
|
|
.master_xfer = mtk_i2c_transfer,
|
|
.functionality = mtk_i2c_functionality,
|
|
};
|
|
|
|
static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c,
|
|
unsigned int *clk_src_div)
|
|
{
|
|
int ret;
|
|
|
|
ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
|
|
if (ret < 0)
|
|
i2c->speed_hz = I2C_DEFAULT_SPEED;
|
|
|
|
ret = of_property_read_u32(np, "clock-div", clk_src_div);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (*clk_src_div == 0)
|
|
return -EINVAL;
|
|
|
|
i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
|
|
i2c->use_push_pull =
|
|
of_property_read_bool(np, "mediatek,use-push-pull");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id;
|
|
int ret = 0;
|
|
struct mtk_i2c *i2c;
|
|
struct clk *clk;
|
|
unsigned int clk_src_div;
|
|
struct resource *res;
|
|
int irq;
|
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
|
|
if (!i2c)
|
|
return -ENOMEM;
|
|
|
|
ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div);
|
|
if (ret)
|
|
return -EINVAL;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
i2c->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(i2c->base))
|
|
return PTR_ERR(i2c->base);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(i2c->pdmabase))
|
|
return PTR_ERR(i2c->pdmabase);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq <= 0)
|
|
return irq;
|
|
|
|
init_completion(&i2c->msg_complete);
|
|
|
|
of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
|
|
if (!of_id)
|
|
return -EINVAL;
|
|
|
|
i2c->dev_comp = of_id->data;
|
|
i2c->adap.dev.of_node = pdev->dev.of_node;
|
|
i2c->dev = &pdev->dev;
|
|
i2c->adap.dev.parent = &pdev->dev;
|
|
i2c->adap.owner = THIS_MODULE;
|
|
i2c->adap.algo = &mtk_i2c_algorithm;
|
|
i2c->adap.quirks = i2c->dev_comp->quirks;
|
|
i2c->adap.timeout = 2 * HZ;
|
|
i2c->adap.retries = 1;
|
|
|
|
if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
|
|
return -EINVAL;
|
|
|
|
i2c->clk_main = devm_clk_get(&pdev->dev, "main");
|
|
if (IS_ERR(i2c->clk_main)) {
|
|
dev_err(&pdev->dev, "cannot get main clock\n");
|
|
return PTR_ERR(i2c->clk_main);
|
|
}
|
|
|
|
i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
|
|
if (IS_ERR(i2c->clk_dma)) {
|
|
dev_err(&pdev->dev, "cannot get dma clock\n");
|
|
return PTR_ERR(i2c->clk_dma);
|
|
}
|
|
|
|
clk = i2c->clk_main;
|
|
if (i2c->have_pmic) {
|
|
i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
|
|
if (IS_ERR(i2c->clk_pmic)) {
|
|
dev_err(&pdev->dev, "cannot get pmic clock\n");
|
|
return PTR_ERR(i2c->clk_pmic);
|
|
}
|
|
clk = i2c->clk_pmic;
|
|
}
|
|
|
|
strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
|
|
|
|
ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to set the speed.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (i2c->dev_comp->support_33bits) {
|
|
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "dma_set_mask return error.\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
ret = mtk_i2c_clock_enable(i2c);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "clock enable failed!\n");
|
|
return ret;
|
|
}
|
|
mtk_i2c_init_hw(i2c);
|
|
mtk_i2c_clock_disable(i2c);
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
|
|
IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev,
|
|
"Request I2C IRQ %d fail\n", irq);
|
|
return ret;
|
|
}
|
|
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
|
ret = i2c_add_adapter(&i2c->adap);
|
|
if (ret)
|
|
return ret;
|
|
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct mtk_i2c *i2c = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int mtk_i2c_resume(struct device *dev)
|
|
{
|
|
struct mtk_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
mtk_i2c_init_hw(i2c);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops mtk_i2c_pm = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
|
|
};
|
|
|
|
static struct platform_driver mtk_i2c_driver = {
|
|
.probe = mtk_i2c_probe,
|
|
.remove = mtk_i2c_remove,
|
|
.driver = {
|
|
.name = I2C_DRV_NAME,
|
|
.pm = &mtk_i2c_pm,
|
|
.of_match_table = of_match_ptr(mtk_i2c_of_match),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mtk_i2c_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
|
|
MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
|