500 lines
13 KiB
C
500 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <soc/qcom/cmd-db.h>
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#include <soc/qcom/rpmh.h>
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#include <soc/qcom/tcs.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#define CLK_RPMH_ARC_EN_OFFSET 0
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#define CLK_RPMH_VRM_EN_OFFSET 4
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/**
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* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
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* @unit: divisor used to convert Hz value to an RPMh msg
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* @width: multiplier used to convert Hz value to an RPMh msg
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* @vcd: virtual clock domain that this bcm belongs to
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* @reserved: reserved to pad the struct
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*/
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struct bcm_db {
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__le32 unit;
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__le16 width;
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u8 vcd;
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u8 reserved;
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};
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/**
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* struct clk_rpmh - individual rpmh clock data structure
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* @hw: handle between common and hardware-specific interfaces
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* @res_name: resource name for the rpmh clock
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* @div: clock divider to compute the clock rate
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* @res_addr: base address of the rpmh resource within the RPMh
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* @res_on_val: rpmh clock enable value
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* @state: rpmh clock requested state
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* @aggr_state: rpmh clock aggregated state
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* @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
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* @valid_state_mask: mask to determine the state of the rpmh clock
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* @unit: divisor to convert rate to rpmh msg in magnitudes of Khz
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* @dev: device to which it is attached
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* @peer: pointer to the clock rpmh sibling
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*/
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struct clk_rpmh {
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struct clk_hw hw;
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const char *res_name;
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u8 div;
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u32 res_addr;
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u32 res_on_val;
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u32 state;
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u32 aggr_state;
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u32 last_sent_aggr_state;
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u32 valid_state_mask;
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u32 unit;
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struct device *dev;
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struct clk_rpmh *peer;
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};
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struct clk_rpmh_desc {
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struct clk_hw **clks;
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size_t num_clks;
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};
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static DEFINE_MUTEX(rpmh_clk_lock);
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#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
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_res_en_offset, _res_on, _div) \
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static struct clk_rpmh _platform##_##_name_active; \
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static struct clk_rpmh _platform##_##_name = { \
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.res_name = _res_name, \
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.res_addr = _res_en_offset, \
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.res_on_val = _res_on, \
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.div = _div, \
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.peer = &_platform##_##_name_active, \
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.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
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BIT(RPMH_ACTIVE_ONLY_STATE) | \
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BIT(RPMH_SLEEP_STATE)), \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpmh_ops, \
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.name = #_name, \
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.parent_data = &(const struct clk_parent_data){ \
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.fw_name = "xo", \
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.name = "xo_board", \
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}, \
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.num_parents = 1, \
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}, \
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}; \
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static struct clk_rpmh _platform##_##_name_active = { \
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.res_name = _res_name, \
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.res_addr = _res_en_offset, \
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.res_on_val = _res_on, \
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.div = _div, \
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.peer = &_platform##_##_name, \
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.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
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BIT(RPMH_ACTIVE_ONLY_STATE)), \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpmh_ops, \
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.name = #_name_active, \
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.parent_data = &(const struct clk_parent_data){ \
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.fw_name = "xo", \
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.name = "xo_board", \
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}, \
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.num_parents = 1, \
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}, \
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}
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#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \
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_res_on, _div) \
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__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
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CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
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#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \
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_div) \
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__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
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CLK_RPMH_VRM_EN_OFFSET, 1, _div)
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#define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \
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static struct clk_rpmh _platform##_##_name = { \
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.res_name = _res_name, \
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.valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \
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.div = 1, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_rpmh_bcm_ops, \
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.name = #_name, \
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}, \
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}
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static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
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{
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return container_of(_hw, struct clk_rpmh, hw);
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}
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static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
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{
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return (c->last_sent_aggr_state & BIT(state))
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!= (c->aggr_state & BIT(state));
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}
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static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
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{
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struct tcs_cmd cmd = { 0 };
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u32 cmd_state, on_val;
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enum rpmh_state state = RPMH_SLEEP_STATE;
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int ret;
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cmd.addr = c->res_addr;
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cmd_state = c->aggr_state;
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on_val = c->res_on_val;
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for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
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if (has_state_changed(c, state)) {
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if (cmd_state & BIT(state))
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cmd.data = on_val;
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ret = rpmh_write_async(c->dev, state, &cmd, 1);
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if (ret) {
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dev_err(c->dev, "set %s state of %s failed: (%d)\n",
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!state ? "sleep" :
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state == RPMH_WAKE_ONLY_STATE ?
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"wake" : "active", c->res_name, ret);
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return ret;
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}
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}
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}
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c->last_sent_aggr_state = c->aggr_state;
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c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
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return 0;
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}
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/*
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* Update state and aggregate state values based on enable value.
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*/
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static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
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bool enable)
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{
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int ret;
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/* Nothing required to be done if already off or on */
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if (enable == c->state)
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return 0;
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c->state = enable ? c->valid_state_mask : 0;
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c->aggr_state = c->state | c->peer->state;
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c->peer->aggr_state = c->aggr_state;
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ret = clk_rpmh_send_aggregate_command(c);
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if (!ret)
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return 0;
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if (ret && enable)
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c->state = 0;
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else if (ret)
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c->state = c->valid_state_mask;
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WARN(1, "clk: %s failed to %s\n", c->res_name,
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enable ? "enable" : "disable");
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return ret;
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}
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static int clk_rpmh_prepare(struct clk_hw *hw)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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int ret = 0;
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mutex_lock(&rpmh_clk_lock);
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ret = clk_rpmh_aggregate_state_send_command(c, true);
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mutex_unlock(&rpmh_clk_lock);
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return ret;
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};
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static void clk_rpmh_unprepare(struct clk_hw *hw)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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mutex_lock(&rpmh_clk_lock);
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clk_rpmh_aggregate_state_send_command(c, false);
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mutex_unlock(&rpmh_clk_lock);
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};
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static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct clk_rpmh *r = to_clk_rpmh(hw);
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/*
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* RPMh clocks have a fixed rate. Return static rate.
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*/
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return prate / r->div;
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}
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static const struct clk_ops clk_rpmh_ops = {
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.prepare = clk_rpmh_prepare,
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.unprepare = clk_rpmh_unprepare,
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.recalc_rate = clk_rpmh_recalc_rate,
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};
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static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
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{
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struct tcs_cmd cmd = { 0 };
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u32 cmd_state;
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int ret;
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mutex_lock(&rpmh_clk_lock);
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cmd_state = 0;
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if (enable) {
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cmd_state = 1;
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if (c->aggr_state)
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cmd_state = c->aggr_state;
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}
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if (c->last_sent_aggr_state == cmd_state) {
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mutex_unlock(&rpmh_clk_lock);
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return 0;
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}
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cmd.addr = c->res_addr;
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cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
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ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1);
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if (ret) {
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dev_err(c->dev, "set active state of %s failed: (%d)\n",
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c->res_name, ret);
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mutex_unlock(&rpmh_clk_lock);
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return ret;
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}
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c->last_sent_aggr_state = cmd_state;
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mutex_unlock(&rpmh_clk_lock);
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return 0;
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}
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static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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return clk_rpmh_bcm_send_cmd(c, true);
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};
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static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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clk_rpmh_bcm_send_cmd(c, false);
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};
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static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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c->aggr_state = rate / c->unit;
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/*
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* Since any non-zero value sent to hw would result in enabling the
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* clock, only send the value if the clock has already been prepared.
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*/
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if (clk_hw_is_prepared(hw))
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clk_rpmh_bcm_send_cmd(c, true);
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return 0;
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};
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static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return rate;
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}
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static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct clk_rpmh *c = to_clk_rpmh(hw);
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return c->aggr_state * c->unit;
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}
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static const struct clk_ops clk_rpmh_bcm_ops = {
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.prepare = clk_rpmh_bcm_prepare,
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.unprepare = clk_rpmh_bcm_unprepare,
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.set_rate = clk_rpmh_bcm_set_rate,
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.round_rate = clk_rpmh_round_rate,
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.recalc_rate = clk_rpmh_bcm_recalc_rate,
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};
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/* Resource name must match resource id present in cmd-db. */
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DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
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DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
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DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
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DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
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DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
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DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
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DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
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static struct clk_hw *sdm845_rpmh_clocks[] = {
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[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
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[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
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[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
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[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
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[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
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[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
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[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
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[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
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[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
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[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
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[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
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[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
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[RPMH_IPA_CLK] = &sdm845_ipa.hw,
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};
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static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
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.clks = sdm845_rpmh_clocks,
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.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
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};
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DEFINE_CLK_RPMH_ARC(sm8150, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
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DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
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DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
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DEFINE_CLK_RPMH_VRM(sm8150, rf_clk1, rf_clk1_ao, "rfclka1", 1);
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DEFINE_CLK_RPMH_VRM(sm8150, rf_clk2, rf_clk2_ao, "rfclka2", 1);
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DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
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static struct clk_hw *sm8150_rpmh_clocks[] = {
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[RPMH_CXO_CLK] = &sm8150_bi_tcxo.hw,
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[RPMH_CXO_CLK_A] = &sm8150_bi_tcxo_ao.hw,
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[RPMH_LN_BB_CLK2] = &sm8150_ln_bb_clk2.hw,
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[RPMH_LN_BB_CLK2_A] = &sm8150_ln_bb_clk2_ao.hw,
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[RPMH_LN_BB_CLK3] = &sm8150_ln_bb_clk3.hw,
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[RPMH_LN_BB_CLK3_A] = &sm8150_ln_bb_clk3_ao.hw,
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[RPMH_RF_CLK1] = &sm8150_rf_clk1.hw,
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[RPMH_RF_CLK1_A] = &sm8150_rf_clk1_ao.hw,
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[RPMH_RF_CLK2] = &sm8150_rf_clk2.hw,
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[RPMH_RF_CLK2_A] = &sm8150_rf_clk2_ao.hw,
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[RPMH_RF_CLK3] = &sm8150_rf_clk3.hw,
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[RPMH_RF_CLK3_A] = &sm8150_rf_clk3_ao.hw,
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};
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static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
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.clks = sm8150_rpmh_clocks,
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.num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
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};
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static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
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void *data)
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{
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struct clk_rpmh_desc *rpmh = data;
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unsigned int idx = clkspec->args[0];
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if (idx >= rpmh->num_clks) {
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pr_err("%s: invalid index %u\n", __func__, idx);
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return ERR_PTR(-EINVAL);
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}
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return rpmh->clks[idx];
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}
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static int clk_rpmh_probe(struct platform_device *pdev)
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{
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struct clk_hw **hw_clks;
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struct clk_rpmh *rpmh_clk;
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const struct clk_rpmh_desc *desc;
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int ret, i;
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desc = of_device_get_match_data(&pdev->dev);
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if (!desc)
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return -ENODEV;
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hw_clks = desc->clks;
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for (i = 0; i < desc->num_clks; i++) {
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const char *name = hw_clks[i]->init->name;
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u32 res_addr;
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size_t aux_data_len;
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const struct bcm_db *data;
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rpmh_clk = to_clk_rpmh(hw_clks[i]);
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res_addr = cmd_db_read_addr(rpmh_clk->res_name);
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if (!res_addr) {
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dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
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rpmh_clk->res_name);
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return -ENODEV;
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}
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data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
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if (IS_ERR(data)) {
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ret = PTR_ERR(data);
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dev_err(&pdev->dev,
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"error reading RPMh aux data for %s (%d)\n",
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rpmh_clk->res_name, ret);
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return ret;
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}
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/* Convert unit from Khz to Hz */
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if (aux_data_len == sizeof(*data))
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rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
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rpmh_clk->res_addr += res_addr;
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rpmh_clk->dev = &pdev->dev;
|
|
|
|
ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to register %s\n", name);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* typecast to silence compiler warning */
|
|
ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
|
|
(void *)desc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to add clock provider\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id clk_rpmh_match_table[] = {
|
|
{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
|
|
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
|
|
|
|
static struct platform_driver clk_rpmh_driver = {
|
|
.probe = clk_rpmh_probe,
|
|
.driver = {
|
|
.name = "clk-rpmh",
|
|
.of_match_table = clk_rpmh_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init clk_rpmh_init(void)
|
|
{
|
|
return platform_driver_register(&clk_rpmh_driver);
|
|
}
|
|
subsys_initcall(clk_rpmh_init);
|
|
|
|
static void __exit clk_rpmh_exit(void)
|
|
{
|
|
platform_driver_unregister(&clk_rpmh_driver);
|
|
}
|
|
module_exit(clk_rpmh_exit);
|
|
|
|
MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
|
|
MODULE_LICENSE("GPL v2");
|