405 lines
10 KiB
C
405 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014-2021 Nuvoton Technology corporation
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* Copyright (C) 2019-2022 Infineon Technologies AG
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*
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* This device driver implements the TPM interface as defined in the TCG PC
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* Client Platform TPM Profile (PTP) Specification for TPM 2.0 v1.04
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* Revision 14.
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*
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* It is based on the tpm_tis_spi device driver.
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*/
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#include <linux/i2c.h>
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#include <linux/crc-ccitt.h>
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#include "tpm_tis_core.h"
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/* TPM registers */
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#define TPM_I2C_LOC_SEL 0x00
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#define TPM_I2C_ACCESS 0x04
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#define TPM_I2C_INTERFACE_CAPABILITY 0x30
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#define TPM_I2C_DEVICE_ADDRESS 0x38
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#define TPM_I2C_DATA_CSUM_ENABLE 0x40
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#define TPM_DATA_CSUM 0x44
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#define TPM_I2C_DID_VID 0x48
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#define TPM_I2C_RID 0x4C
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/* TIS-compatible register address to avoid clash with TPM_ACCESS (0x00) */
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#define TPM_LOC_SEL 0x0FFF
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/* Mask to extract the I2C register from TIS register addresses */
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#define TPM_TIS_REGISTER_MASK 0x0FFF
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/* Default Guard Time of 250µs until interface capability register is read */
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#define GUARD_TIME_DEFAULT_MIN 250
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#define GUARD_TIME_DEFAULT_MAX 300
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/* Guard Time of 250µs after I2C slave NACK */
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#define GUARD_TIME_ERR_MIN 250
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#define GUARD_TIME_ERR_MAX 300
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/* Guard Time bit masks; SR is repeated start, RW is read then write, etc. */
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#define TPM_GUARD_TIME_SR_MASK 0x40000000
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#define TPM_GUARD_TIME_RR_MASK 0x00100000
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#define TPM_GUARD_TIME_RW_MASK 0x00080000
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#define TPM_GUARD_TIME_WR_MASK 0x00040000
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#define TPM_GUARD_TIME_WW_MASK 0x00020000
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#define TPM_GUARD_TIME_MIN_MASK 0x0001FE00
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#define TPM_GUARD_TIME_MIN_SHIFT 9
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/* Masks with bits that must be read zero */
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#define TPM_ACCESS_READ_ZERO 0x48
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#define TPM_INT_ENABLE_ZERO 0x7FFFFF60
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#define TPM_STS_READ_ZERO 0x23
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#define TPM_INTF_CAPABILITY_ZERO 0x0FFFF000
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#define TPM_I2C_INTERFACE_CAPABILITY_ZERO 0x80000000
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struct tpm_tis_i2c_phy {
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struct tpm_tis_data priv;
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struct i2c_client *i2c_client;
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bool guard_time_read;
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bool guard_time_write;
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u16 guard_time_min;
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u16 guard_time_max;
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u8 *io_buf;
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};
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static inline struct tpm_tis_i2c_phy *
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to_tpm_tis_i2c_phy(struct tpm_tis_data *data)
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{
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return container_of(data, struct tpm_tis_i2c_phy, priv);
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}
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/*
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* tpm_tis_core uses the register addresses as defined in Table 19 "Allocation
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* of Register Space for FIFO TPM Access" of the TCG PC Client PTP
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* Specification. In order for this code to work together with tpm_tis_core,
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* those addresses need to mapped to the registers defined for I2C TPMs in
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* Table 51 "I2C-TPM Register Overview".
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*
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* For most addresses this can be done by simply stripping off the locality
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* information from the address. A few addresses need to be mapped explicitly,
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* since the corresponding I2C registers have been moved around. TPM_LOC_SEL is
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* only defined for I2C TPMs and is also mapped explicitly here to distinguish
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* it from TPM_ACCESS(0).
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*
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* Locality information is ignored, since this driver assumes exclusive access
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* to the TPM and always uses locality 0.
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*/
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static u8 tpm_tis_i2c_address_to_register(u32 addr)
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{
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addr &= TPM_TIS_REGISTER_MASK;
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switch (addr) {
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case TPM_ACCESS(0):
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return TPM_I2C_ACCESS;
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case TPM_LOC_SEL:
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return TPM_I2C_LOC_SEL;
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case TPM_DID_VID(0):
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return TPM_I2C_DID_VID;
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case TPM_RID(0):
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return TPM_I2C_RID;
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default:
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return addr;
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}
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}
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static int tpm_tis_i2c_retry_transfer_until_ack(struct tpm_tis_data *data,
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struct i2c_msg *msg)
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{
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struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
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bool guard_time;
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int i = 0;
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int ret;
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if (msg->flags & I2C_M_RD)
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guard_time = phy->guard_time_read;
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else
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guard_time = phy->guard_time_write;
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do {
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ret = i2c_transfer(phy->i2c_client->adapter, msg, 1);
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if (ret < 0)
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usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
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else if (guard_time)
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usleep_range(phy->guard_time_min, phy->guard_time_max);
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/* retry on TPM NACK */
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} while (ret < 0 && i++ < TPM_RETRY);
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return ret;
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}
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/* Check that bits which must be read zero are not set */
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static int tpm_tis_i2c_sanity_check_read(u8 reg, u16 len, u8 *buf)
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{
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u32 zero_mask;
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u32 value;
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switch (len) {
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case sizeof(u8):
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value = buf[0];
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break;
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case sizeof(u16):
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value = le16_to_cpup((__le16 *)buf);
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break;
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case sizeof(u32):
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value = le32_to_cpup((__le32 *)buf);
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break;
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default:
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/* unknown length, skip check */
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return 0;
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}
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switch (reg) {
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case TPM_I2C_ACCESS:
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zero_mask = TPM_ACCESS_READ_ZERO;
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break;
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case TPM_INT_ENABLE(0) & TPM_TIS_REGISTER_MASK:
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zero_mask = TPM_INT_ENABLE_ZERO;
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break;
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case TPM_STS(0) & TPM_TIS_REGISTER_MASK:
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zero_mask = TPM_STS_READ_ZERO;
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break;
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case TPM_INTF_CAPS(0) & TPM_TIS_REGISTER_MASK:
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zero_mask = TPM_INTF_CAPABILITY_ZERO;
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break;
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case TPM_I2C_INTERFACE_CAPABILITY:
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zero_mask = TPM_I2C_INTERFACE_CAPABILITY_ZERO;
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break;
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default:
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/* unknown register, skip check */
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return 0;
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}
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if (unlikely((value & zero_mask) != 0x00)) {
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pr_debug("TPM I2C read of register 0x%02x failed sanity check: 0x%x\n", reg, value);
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return -EIO;
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}
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return 0;
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}
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static int tpm_tis_i2c_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
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u8 *result, enum tpm_tis_io_mode io_mode)
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{
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struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
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struct i2c_msg msg = { .addr = phy->i2c_client->addr };
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u8 reg = tpm_tis_i2c_address_to_register(addr);
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int i;
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int ret;
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for (i = 0; i < TPM_RETRY; i++) {
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u16 read = 0;
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while (read < len) {
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/* write register */
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msg.len = sizeof(reg);
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msg.buf = ®
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msg.flags = 0;
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ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
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if (ret < 0)
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return ret;
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/* read data */
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msg.buf = result + read;
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msg.len = len - read;
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msg.flags = I2C_M_RD;
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if (msg.len > I2C_SMBUS_BLOCK_MAX)
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msg.len = I2C_SMBUS_BLOCK_MAX;
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ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
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if (ret < 0)
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return ret;
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read += msg.len;
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}
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ret = tpm_tis_i2c_sanity_check_read(reg, len, result);
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if (ret == 0)
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return 0;
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usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
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}
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return ret;
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}
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static int tpm_tis_i2c_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
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const u8 *value,
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enum tpm_tis_io_mode io_mode)
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{
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struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
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struct i2c_msg msg = { .addr = phy->i2c_client->addr };
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u8 reg = tpm_tis_i2c_address_to_register(addr);
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int ret;
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u16 wrote = 0;
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if (len > TPM_BUFSIZE - 1)
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return -EIO;
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phy->io_buf[0] = reg;
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msg.buf = phy->io_buf;
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while (wrote < len) {
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/* write register and data in one go */
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msg.len = sizeof(reg) + len - wrote;
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if (msg.len > I2C_SMBUS_BLOCK_MAX)
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msg.len = I2C_SMBUS_BLOCK_MAX;
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memcpy(phy->io_buf + sizeof(reg), value + wrote,
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msg.len - sizeof(reg));
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ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
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if (ret < 0)
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return ret;
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wrote += msg.len - sizeof(reg);
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}
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return 0;
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}
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static int tpm_tis_i2c_verify_crc(struct tpm_tis_data *data, size_t len,
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const u8 *value)
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{
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u16 crc_tpm, crc_host;
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int rc;
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rc = tpm_tis_read16(data, TPM_DATA_CSUM, &crc_tpm);
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if (rc < 0)
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return rc;
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/* reflect crc result, regardless of host endianness */
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crc_host = swab16(crc_ccitt(0, value, len));
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if (crc_tpm != crc_host)
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return -EIO;
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return 0;
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}
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/*
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* Guard Time:
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* After each I2C operation, the TPM might require the master to wait.
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* The time period is vendor-specific and must be read from the
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* TPM_I2C_INTERFACE_CAPABILITY register.
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*
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* Before the Guard Time is read (or after the TPM failed to send an I2C NACK),
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* a Guard Time of 250µs applies.
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*
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* Various flags in the same register indicate if a guard time is needed:
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* - SR: <I2C read with repeated start> <guard time> <I2C read>
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* - RR: <I2C read> <guard time> <I2C read>
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* - RW: <I2C read> <guard time> <I2C write>
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* - WR: <I2C write> <guard time> <I2C read>
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* - WW: <I2C write> <guard time> <I2C write>
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*
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* See TCG PC Client PTP Specification v1.04, 8.1.10 GUARD_TIME
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*/
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static int tpm_tis_i2c_init_guard_time(struct tpm_tis_i2c_phy *phy)
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{
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u32 i2c_caps;
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int ret;
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phy->guard_time_read = true;
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phy->guard_time_write = true;
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phy->guard_time_min = GUARD_TIME_DEFAULT_MIN;
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phy->guard_time_max = GUARD_TIME_DEFAULT_MAX;
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ret = tpm_tis_i2c_read_bytes(&phy->priv, TPM_I2C_INTERFACE_CAPABILITY,
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sizeof(i2c_caps), (u8 *)&i2c_caps,
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TPM_TIS_PHYS_32);
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if (ret)
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return ret;
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phy->guard_time_read = (i2c_caps & TPM_GUARD_TIME_RR_MASK) ||
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(i2c_caps & TPM_GUARD_TIME_RW_MASK);
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phy->guard_time_write = (i2c_caps & TPM_GUARD_TIME_WR_MASK) ||
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(i2c_caps & TPM_GUARD_TIME_WW_MASK);
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phy->guard_time_min = (i2c_caps & TPM_GUARD_TIME_MIN_MASK) >>
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TPM_GUARD_TIME_MIN_SHIFT;
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/* guard_time_max = guard_time_min * 1.2 */
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phy->guard_time_max = phy->guard_time_min + phy->guard_time_min / 5;
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
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static const struct tpm_tis_phy_ops tpm_i2c_phy_ops = {
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.read_bytes = tpm_tis_i2c_read_bytes,
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.write_bytes = tpm_tis_i2c_write_bytes,
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.verify_crc = tpm_tis_i2c_verify_crc,
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};
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static int tpm_tis_i2c_probe(struct i2c_client *dev)
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{
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struct tpm_tis_i2c_phy *phy;
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const u8 crc_enable = 1;
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const u8 locality = 0;
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int ret;
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phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_i2c_phy),
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GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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phy->io_buf = devm_kzalloc(&dev->dev, TPM_BUFSIZE, GFP_KERNEL);
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if (!phy->io_buf)
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return -ENOMEM;
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set_bit(TPM_TIS_DEFAULT_CANCELLATION, &phy->priv.flags);
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phy->i2c_client = dev;
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/* must precede all communication with the tpm */
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ret = tpm_tis_i2c_init_guard_time(phy);
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if (ret)
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return ret;
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ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_LOC_SEL, sizeof(locality),
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&locality, TPM_TIS_PHYS_8);
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if (ret)
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return ret;
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ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_I2C_DATA_CSUM_ENABLE,
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sizeof(crc_enable), &crc_enable,
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TPM_TIS_PHYS_8);
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if (ret)
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return ret;
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return tpm_tis_core_init(&dev->dev, &phy->priv, -1, &tpm_i2c_phy_ops,
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NULL);
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}
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static void tpm_tis_i2c_remove(struct i2c_client *client)
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{
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struct tpm_chip *chip = i2c_get_clientdata(client);
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tpm_chip_unregister(chip);
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tpm_tis_remove(chip);
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}
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static const struct i2c_device_id tpm_tis_i2c_id[] = {
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{ "tpm_tis_i2c", 0 },
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{}
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};
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MODULE_DEVICE_TABLE(i2c, tpm_tis_i2c_id);
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#ifdef CONFIG_OF
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static const struct of_device_id of_tis_i2c_match[] = {
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{ .compatible = "infineon,slb9673", },
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{}
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};
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MODULE_DEVICE_TABLE(of, of_tis_i2c_match);
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#endif
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static struct i2c_driver tpm_tis_i2c_driver = {
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.driver = {
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.name = "tpm_tis_i2c",
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.pm = &tpm_tis_pm,
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.of_match_table = of_match_ptr(of_tis_i2c_match),
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},
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.probe = tpm_tis_i2c_probe,
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.remove = tpm_tis_i2c_remove,
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.id_table = tpm_tis_i2c_id,
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};
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module_i2c_driver(tpm_tis_i2c_driver);
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MODULE_DESCRIPTION("TPM Driver for native I2C access");
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MODULE_LICENSE("GPL");
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