340 lines
13 KiB
C
340 lines
13 KiB
C
/*
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* net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __MV88E6XXX_H
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#define __MV88E6XXX_H
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#define SMI_CMD 0x00
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#define SMI_CMD_BUSY BIT(15)
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#define SMI_CMD_CLAUSE_22 BIT(12)
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#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
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#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
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#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
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#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
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#define SMI_DATA 0x01
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#define REG_PORT(p) (0x10 + (p))
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#define PORT_STATUS 0x00
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#define PORT_STATUS_PAUSE_EN BIT(15)
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#define PORT_STATUS_MY_PAUSE BIT(14)
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#define PORT_STATUS_HD_FLOW BIT(13)
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#define PORT_STATUS_PHY_DETECT BIT(12)
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#define PORT_STATUS_LINK BIT(11)
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#define PORT_STATUS_DUPLEX BIT(10)
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#define PORT_STATUS_SPEED_MASK 0x0300
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#define PORT_STATUS_SPEED_10 0x0000
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#define PORT_STATUS_SPEED_100 0x0100
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#define PORT_STATUS_SPEED_1000 0x0200
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#define PORT_STATUS_EEE BIT(6) /* 6352 */
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#define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
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#define PORT_STATUS_MGMII BIT(6) /* 6185 */
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#define PORT_STATUS_TX_PAUSED BIT(5)
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#define PORT_STATUS_FLOW_CTRL BIT(4)
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#define PORT_PCS_CTRL 0x01
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#define PORT_SWITCH_ID 0x03
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#define PORT_SWITCH_ID_6085 0x04a0
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#define PORT_SWITCH_ID_6095 0x0950
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#define PORT_SWITCH_ID_6123 0x1210
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#define PORT_SWITCH_ID_6123_A1 0x1212
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#define PORT_SWITCH_ID_6123_A2 0x1213
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#define PORT_SWITCH_ID_6131 0x1060
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#define PORT_SWITCH_ID_6131_B2 0x1066
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#define PORT_SWITCH_ID_6152 0x1a40
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#define PORT_SWITCH_ID_6155 0x1a50
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#define PORT_SWITCH_ID_6161 0x1610
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#define PORT_SWITCH_ID_6161_A1 0x1612
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#define PORT_SWITCH_ID_6161_A2 0x1613
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#define PORT_SWITCH_ID_6165 0x1650
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#define PORT_SWITCH_ID_6165_A1 0x1652
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#define PORT_SWITCH_ID_6165_A2 0x1653
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#define PORT_SWITCH_ID_6171 0x1710
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#define PORT_SWITCH_ID_6172 0x1720
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#define PORT_SWITCH_ID_6176 0x1760
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#define PORT_SWITCH_ID_6182 0x1a60
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#define PORT_SWITCH_ID_6185 0x1a70
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#define PORT_SWITCH_ID_6352 0x3520
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#define PORT_SWITCH_ID_6352_A0 0x3521
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#define PORT_SWITCH_ID_6352_A1 0x3522
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#define PORT_CONTROL 0x04
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#define PORT_CONTROL_STATE_MASK 0x03
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#define PORT_CONTROL_STATE_DISABLED 0x00
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#define PORT_CONTROL_STATE_BLOCKING 0x01
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#define PORT_CONTROL_STATE_LEARNING 0x02
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#define PORT_CONTROL_STATE_FORWARDING 0x03
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#define PORT_CONTROL_1 0x05
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#define PORT_BASE_VLAN 0x06
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#define PORT_DEFAULT_VLAN 0x07
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#define PORT_CONTROL_2 0x08
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#define PORT_RATE_CONTROL 0x09
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#define PORT_RATE_CONTROL_2 0x0a
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#define PORT_ASSOC_VECTOR 0x0b
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#define PORT_IN_DISCARD_LO 0x10
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#define PORT_IN_DISCARD_HI 0x11
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#define PORT_IN_FILTERED 0x12
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#define PORT_OUT_FILTERED 0x13
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#define PORT_TAG_REGMAP_0123 0x19
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#define PORT_TAG_REGMAP_4567 0x1a
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#define REG_GLOBAL 0x1b
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#define GLOBAL_STATUS 0x00
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#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
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/* Two bits for 6165, 6185 etc */
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#define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
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#define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
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#define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
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#define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
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#define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
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#define GLOBAL_MAC_01 0x01
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#define GLOBAL_MAC_23 0x02
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#define GLOBAL_MAC_45 0x03
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#define GLOBAL_CONTROL 0x04
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#define GLOBAL_CONTROL_SW_RESET BIT(15)
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#define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
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#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
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#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
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#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
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#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
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#define GLOBAL_CONTROL_DEVICE_EN BIT(7)
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#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
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#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
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#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
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#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
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#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
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#define GLOBAL_CONTROL_TCAM_EN BIT(1)
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#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
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#define GLOBAL_VTU_OP 0x05
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#define GLOBAL_VTU_VID 0x06
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#define GLOBAL_VTU_DATA_0_3 0x07
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#define GLOBAL_VTU_DATA_4_7 0x08
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#define GLOBAL_VTU_DATA_8_11 0x09
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#define GLOBAL_ATU_CONTROL 0x0a
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#define GLOBAL_ATU_OP 0x0b
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#define GLOBAL_ATU_OP_BUSY BIT(15)
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#define GLOBAL_ATU_OP_NOP (0 << 12)
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#define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_FLUSH_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
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#define GLOBAL_ATU_DATA 0x0c
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#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
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#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
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#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
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#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
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#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
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#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
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#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
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#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
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#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
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#define GLOBAL_ATU_MAC_01 0x0d
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#define GLOBAL_ATU_MAC_23 0x0e
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#define GLOBAL_ATU_MAC_45 0x0f
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#define GLOBAL_IP_PRI_0 0x10
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#define GLOBAL_IP_PRI_1 0x11
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#define GLOBAL_IP_PRI_2 0x12
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#define GLOBAL_IP_PRI_3 0x13
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#define GLOBAL_IP_PRI_4 0x14
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#define GLOBAL_IP_PRI_5 0x15
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#define GLOBAL_IP_PRI_6 0x16
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#define GLOBAL_IP_PRI_7 0x17
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#define GLOBAL_IEEE_PRI 0x18
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#define GLOBAL_CORE_TAG_TYPE 0x19
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#define GLOBAL_MONITOR_CONTROL 0x1a
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#define GLOBAL_CONTROL_2 0x1c
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#define GLOBAL_STATS_OP 0x1d
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#define GLOBAL_STATS_OP_BUSY BIT(15)
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#define GLOBAL_STATS_OP_NOP (0 << 12)
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#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
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#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
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#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
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#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
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#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
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#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
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#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
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#define GLOBAL_STATS_COUNTER_32 0x1e
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#define GLOBAL_STATS_COUNTER_01 0x1f
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#define REG_GLOBAL2 0x1c
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#define GLOBAL2_INT_SOURCE 0x00
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#define GLOBAL2_INT_MASK 0x01
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#define GLOBAL2_MGMT_EN_2X 0x02
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#define GLOBAL2_MGMT_EN_0X 0x03
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#define GLOBAL2_FLOW_CONTROL 0x04
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#define GLOBAL2_SWITCH_MGMT 0x05
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#define GLOBAL2_DEVICE_MAPPING 0x06
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#define GLOBAL2_TRUNK_MASK 0x07
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#define GLOBAL2_TRUNK_MAPPING 0x08
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#define GLOBAL2_INGRESS_OP 0x09
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#define GLOBAL2_INGRESS_DATA 0x0a
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#define GLOBAL2_PVT_ADDR 0x0b
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#define GLOBAL2_PVT_DATA 0x0c
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#define GLOBAL2_SWITCH_MAC 0x0d
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#define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
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#define GLOBAL2_ATU_STATS 0x0e
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#define GLOBAL2_PRIO_OVERRIDE 0x0f
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#define GLOBAL2_EEPROM_OP 0x14
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#define GLOBAL2_EEPROM_OP_BUSY BIT(15)
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#define GLOBAL2_EEPROM_OP_LOAD BIT(11)
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#define GLOBAL2_EEPROM_DATA 0x15
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#define GLOBAL2_PTP_AVB_OP 0x16
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#define GLOBAL2_PTP_AVB_DATA 0x17
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#define GLOBAL2_SMI_OP 0x18
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#define GLOBAL2_SMI_OP_BUSY BIT(15)
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#define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12)
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#define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
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GLOBAL2_SMI_OP_CLAUSE_22)
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#define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
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GLOBAL2_SMI_OP_CLAUSE_22)
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#define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY)
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#define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY)
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#define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY)
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#define GLOBAL2_SMI_DATA 0x19
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#define GLOBAL2_SCRATCH_MISC 0x1a
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#define GLOBAL2_WDOG_CONTROL 0x1b
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#define GLOBAL2_QOS_WEIGHT 0x1c
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#define GLOBAL2_MISC 0x1d
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struct mv88e6xxx_priv_state {
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/* When using multi-chip addressing, this mutex protects
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* access to the indirect access registers. (In single-chip
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* mode, this mutex is effectively useless.)
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*/
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struct mutex smi_mutex;
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#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
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/* Handles automatic disabling and re-enabling of the PHY
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* polling unit.
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*/
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struct mutex ppu_mutex;
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int ppu_disabled;
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struct work_struct ppu_work;
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struct timer_list ppu_timer;
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#endif
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/* This mutex serialises access to the statistics unit.
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* Hold this mutex over snapshot + dump sequences.
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*/
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struct mutex stats_mutex;
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/* This mutex serializes phy access for chips with
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* indirect phy addressing. It is unused for chips
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* with direct phy access.
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*/
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struct mutex phy_mutex;
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/* This mutex serializes eeprom access for chips with
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* eeprom support.
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*/
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struct mutex eeprom_mutex;
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int id; /* switch product id */
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int num_ports; /* number of switch ports */
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/* hw bridging */
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u32 fid_mask;
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u8 fid[DSA_MAX_PORTS];
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u16 bridge_mask[DSA_MAX_PORTS];
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unsigned long port_state_update_mask;
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u8 port_state[DSA_MAX_PORTS];
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struct work_struct bridge_work;
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};
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struct mv88e6xxx_hw_stat {
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char string[ETH_GSTRING_LEN];
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int sizeof_stat;
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int reg;
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};
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int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active);
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int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port);
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int mv88e6xxx_setup_common(struct dsa_switch *ds);
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int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
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int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
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int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
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int reg, u16 val);
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int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
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int mv88e6xxx_config_prio(struct dsa_switch *ds);
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int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr);
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int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr);
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int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
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int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
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int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum);
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int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
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u16 val);
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void mv88e6xxx_ppu_state_init(struct dsa_switch *ds);
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int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum);
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int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
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int regnum, u16 val);
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void mv88e6xxx_poll_link(struct dsa_switch *ds);
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void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data);
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void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
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uint64_t *data);
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int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
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int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
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int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
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void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
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struct ethtool_regs *regs, void *_p);
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int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp);
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int mv88e6xxx_phy_wait(struct dsa_switch *ds);
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int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds);
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int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds);
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int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum);
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int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
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u16 val);
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int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
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int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
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struct phy_device *phydev, struct ethtool_eee *e);
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int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
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int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
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int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state);
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int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
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const unsigned char *addr, u16 vid);
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int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
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const unsigned char *addr, u16 vid);
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int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
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unsigned char *addr, bool *is_static);
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int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
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int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
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int reg, int val);
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extern struct dsa_switch_driver mv88e6131_switch_driver;
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extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;
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extern struct dsa_switch_driver mv88e6352_switch_driver;
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extern struct dsa_switch_driver mv88e6171_switch_driver;
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#define REG_READ(addr, reg) \
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({ \
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int __ret; \
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\
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__ret = mv88e6xxx_reg_read(ds, addr, reg); \
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if (__ret < 0) \
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return __ret; \
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__ret; \
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})
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#define REG_WRITE(addr, reg, val) \
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({ \
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int __ret; \
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\
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__ret = mv88e6xxx_reg_write(ds, addr, reg, val); \
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if (__ret < 0) \
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return __ret; \
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})
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#endif
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