122 lines
2.4 KiB
Plaintext
122 lines
2.4 KiB
Plaintext
/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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/ {
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model = "Qualcomm MSM8974";
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compatible = "qcom,msm8974";
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interrupt-parent = <&intc>;
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@f9000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0xf9000000 0x1000>,
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<0xf9002000 0x1000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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<1 3 0xf08>,
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<1 4 0xf08>,
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<1 1 0xf08>;
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clock-frequency = <19200000>;
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};
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timer@f9020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf9020000 0x1000>;
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clock-frequency = <19200000>;
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frame@f9021000 {
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frame-number = <0>;
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interrupts = <0 8 0x4>,
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<0 7 0x4>;
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reg = <0xf9021000 0x1000>,
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<0xf9022000 0x1000>;
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};
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frame@f9023000 {
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frame-number = <1>;
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interrupts = <0 9 0x4>;
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reg = <0xf9023000 0x1000>;
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status = "disabled";
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};
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frame@f9024000 {
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frame-number = <2>;
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interrupts = <0 10 0x4>;
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reg = <0xf9024000 0x1000>;
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status = "disabled";
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};
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frame@f9025000 {
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frame-number = <3>;
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interrupts = <0 11 0x4>;
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reg = <0xf9025000 0x1000>;
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status = "disabled";
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};
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frame@f9026000 {
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frame-number = <4>;
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interrupts = <0 12 0x4>;
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reg = <0xf9026000 0x1000>;
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status = "disabled";
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};
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frame@f9027000 {
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frame-number = <5>;
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interrupts = <0 13 0x4>;
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reg = <0xf9027000 0x1000>;
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status = "disabled";
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};
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frame@f9028000 {
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frame-number = <6>;
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interrupts = <0 14 0x4>;
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reg = <0xf9028000 0x1000>;
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status = "disabled";
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};
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};
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restart@fc4ab000 {
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compatible = "qcom,pshold";
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reg = <0xfc4ab000 0x4>;
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};
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gcc: clock-controller@fc400000 {
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compatible = "qcom,gcc-msm8974";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0xfc400000 0x4000>;
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};
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mmcc: clock-controller@fd8c0000 {
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compatible = "qcom,mmcc-msm8974";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0xfd8c0000 0x6000>;
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};
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serial@f991e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf991e000 0x1000>;
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interrupts = <0 108 0x0>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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};
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};
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};
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