230 lines
6.1 KiB
C
230 lines
6.1 KiB
C
/*
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* Rockchip emmc PHY driver
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*
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* Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
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* Copyright (C) 2016 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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/*
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* The higher 16-bit of this register is used for write protection
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* only if BIT(x + 16) set to 1 the BIT(x) can be written.
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*/
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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/* Register definition */
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#define GRF_EMMCPHY_CON0 0x0
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#define GRF_EMMCPHY_CON1 0x4
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#define GRF_EMMCPHY_CON2 0x8
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#define GRF_EMMCPHY_CON3 0xc
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#define GRF_EMMCPHY_CON4 0x10
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#define GRF_EMMCPHY_CON5 0x14
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#define GRF_EMMCPHY_CON6 0x18
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#define GRF_EMMCPHY_STATUS 0x20
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#define PHYCTRL_PDB_MASK 0x1
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#define PHYCTRL_PDB_SHIFT 0x0
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#define PHYCTRL_PDB_PWR_ON 0x1
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#define PHYCTRL_PDB_PWR_OFF 0x0
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#define PHYCTRL_ENDLL_MASK 0x1
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#define PHYCTRL_ENDLL_SHIFT 0x1
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#define PHYCTRL_ENDLL_ENABLE 0x1
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#define PHYCTRL_ENDLL_DISABLE 0x0
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#define PHYCTRL_CALDONE_MASK 0x1
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#define PHYCTRL_CALDONE_SHIFT 0x6
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#define PHYCTRL_CALDONE_DONE 0x1
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#define PHYCTRL_CALDONE_GOING 0x0
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#define PHYCTRL_DLLRDY_MASK 0x1
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#define PHYCTRL_DLLRDY_SHIFT 0x5
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#define PHYCTRL_DLLRDY_DONE 0x1
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#define PHYCTRL_DLLRDY_GOING 0x0
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struct rockchip_emmc_phy {
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unsigned int reg_offset;
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struct regmap *reg_base;
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};
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static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
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bool on_off)
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{
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unsigned int caldone;
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unsigned int dllrdy;
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/*
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* Keep phyctrl_pdb and phyctrl_endll low to allow
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* initialization of CALIO state M/C DFFs
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*/
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON6,
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HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
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PHYCTRL_PDB_MASK,
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PHYCTRL_PDB_SHIFT));
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON6,
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HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
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PHYCTRL_ENDLL_MASK,
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PHYCTRL_ENDLL_SHIFT));
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/* Already finish power_off above */
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if (on_off == PHYCTRL_PDB_PWR_OFF)
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return 0;
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/*
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* According to the user manual, calpad calibration
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* cycle takes more than 2us without the minimal recommended
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* value, so we may need a little margin here
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*/
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udelay(3);
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON6,
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HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
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PHYCTRL_PDB_MASK,
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PHYCTRL_PDB_SHIFT));
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/*
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* According to the user manual, it asks driver to
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* wait 5us for calpad busy trimming
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*/
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udelay(5);
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regmap_read(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
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&caldone);
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caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
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if (caldone != PHYCTRL_CALDONE_DONE) {
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pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
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return -ETIMEDOUT;
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}
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regmap_write(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_CON6,
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HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
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PHYCTRL_ENDLL_MASK,
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PHYCTRL_ENDLL_SHIFT));
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/*
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* After enable analog DLL circuits, we need extra 10.2us
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* for dll to be ready for work.
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*/
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udelay(11);
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regmap_read(rk_phy->reg_base,
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rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
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&dllrdy);
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dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
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if (dllrdy != PHYCTRL_DLLRDY_DONE) {
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pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int rockchip_emmc_phy_power_off(struct phy *phy)
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{
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
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int ret = 0;
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/* Power down emmc phy analog blocks */
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ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
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if (ret)
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return ret;
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return 0;
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}
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static int rockchip_emmc_phy_power_on(struct phy *phy)
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{
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
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int ret = 0;
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/* Power up emmc phy analog blocks */
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ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
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if (ret)
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return ret;
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return 0;
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}
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static const struct phy_ops ops = {
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.power_on = rockchip_emmc_phy_power_on,
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.power_off = rockchip_emmc_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int rockchip_emmc_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rockchip_emmc_phy *rk_phy;
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struct phy *generic_phy;
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struct phy_provider *phy_provider;
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struct regmap *grf;
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unsigned int reg_offset;
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grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
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if (IS_ERR(grf)) {
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dev_err(dev, "Missing rockchip,grf property\n");
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return PTR_ERR(grf);
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}
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rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
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if (!rk_phy)
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return -ENOMEM;
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if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
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dev_err(dev, "missing reg property in node %s\n",
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dev->of_node->name);
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return -EINVAL;
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}
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rk_phy->reg_offset = reg_offset;
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rk_phy->reg_base = grf;
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generic_phy = devm_phy_create(dev, dev->of_node, &ops);
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if (IS_ERR(generic_phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(generic_phy);
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}
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phy_set_drvdata(generic_phy, rk_phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
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{ .compatible = "rockchip,rk3399-emmc-phy" },
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{}
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};
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MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
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static struct platform_driver rockchip_emmc_driver = {
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.probe = rockchip_emmc_phy_probe,
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.driver = {
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.name = "rockchip-emmc-phy",
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.of_match_table = rockchip_emmc_phy_dt_ids,
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},
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};
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module_platform_driver(rockchip_emmc_driver);
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MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
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MODULE_LICENSE("GPL v2");
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