230 lines
5.6 KiB
C
230 lines
5.6 KiB
C
/*
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* Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Li Yang <LeoLi@freescale.com>
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* Yin Olivia <Hong-hua.Yin@freescale.com>
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*
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* Description:
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* MPC8360E MDS board specific routines.
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*
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* Changelog:
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* Jun 21, 2006 Initial version
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/initrd.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ipic.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/simple_gpio.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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#include "mpc83xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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static void __init mpc836x_mds_setup_arch(void)
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{
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struct device_node *np;
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u8 __iomem *bcsr_regs = NULL;
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if (ppc_md.progress)
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ppc_md.progress("mpc836x_mds_setup_arch()", 0);
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/* Map BCSR area */
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np = of_find_node_by_name(NULL, "bcsr");
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if (np) {
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struct resource res;
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of_address_to_resource(np, 0, &res);
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bcsr_regs = ioremap(res.start, resource_size(&res));
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of_node_put(np);
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}
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mpc83xx_setup_pci();
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#ifdef CONFIG_QUICC_ENGINE
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qe_reset();
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if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
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par_io_init(np);
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of_node_put(np);
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for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
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par_io_of_config(np);
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#ifdef CONFIG_QE_USB
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/* Must fixup Par IO before QE GPIO chips are registered. */
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par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
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par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
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par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
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par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
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par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
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par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
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par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
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#endif /* CONFIG_QE_USB */
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}
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if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
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!= NULL){
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uint svid;
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/* Reset the Ethernet PHY */
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#define BCSR9_GETHRST 0x20
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clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
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udelay(1000);
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setbits8(&bcsr_regs[9], BCSR9_GETHRST);
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/* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
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svid = mfspr(SPRN_SVR);
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if (svid == 0x80480021) {
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void __iomem *immap;
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immap = ioremap(get_immrbase() + 0x14a8, 8);
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/*
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* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
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* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
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*/
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setbits32(immap, 0x0c003000);
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/*
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* IMMR + 0x14AC[20:27] = 10101010
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* (data delay for both UCC's)
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*/
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clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
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iounmap(immap);
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}
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iounmap(bcsr_regs);
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of_node_put(np);
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}
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#endif /* CONFIG_QUICC_ENGINE */
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}
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machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
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#ifdef CONFIG_QE_USB
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static int __init mpc836x_usb_cfg(void)
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{
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u8 __iomem *bcsr;
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struct device_node *np;
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const char *mode;
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int ret = 0;
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
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if (!np)
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return -ENODEV;
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bcsr = of_iomap(np, 0);
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of_node_put(np);
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if (!bcsr)
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return -ENOMEM;
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
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if (!np) {
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ret = -ENODEV;
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goto err;
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}
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#define BCSR8_TSEC1M_MASK (0x3 << 6)
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#define BCSR8_TSEC1M_RGMII (0x0 << 6)
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#define BCSR8_TSEC2M_MASK (0x3 << 4)
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#define BCSR8_TSEC2M_RGMII (0x0 << 4)
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/*
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* Default is GMII (2), but we should set it to RGMII (0) if we use
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* USB (Eth PHY is in RGMII mode anyway).
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*/
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clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
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BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
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#define BCSR13_USBMASK 0x0f
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#define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */
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#define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */
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#define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */
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#define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */
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clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
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mode = of_get_property(np, "mode", NULL);
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if (mode && !strcmp(mode, "peripheral")) {
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setbits8(&bcsr[13], BCSR13_nUSBVCC);
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qe_usb_clock_set(QE_CLK21, 48000000);
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} else {
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setbits8(&bcsr[13], BCSR13_USBMODE);
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/*
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* The BCSR GPIOs are used to control power and
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* speed of the USB transceiver. This is needed for
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* the USB Host only.
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*/
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simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
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}
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of_node_put(np);
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err:
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iounmap(bcsr);
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return ret;
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}
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machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
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#endif /* CONFIG_QE_USB */
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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*/
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static int __init mpc836x_mds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC836xMDS");
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}
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define_machine(mpc836x_mds) {
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.name = "MPC836x MDS",
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.probe = mpc836x_mds_probe,
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.setup_arch = mpc836x_mds_setup_arch,
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.init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
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.get_irq = ipic_get_irq,
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.restart = mpc83xx_restart,
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.time_init = mpc83xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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