441 lines
12 KiB
C
441 lines
12 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for HDA DSP code loader
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*/
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#include <linux/firmware.h>
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#include <sound/hdaudio_ext.h>
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#include <sound/sof.h>
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#include "../ops.h"
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#include "hda.h"
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#define HDA_FW_BOOT_ATTEMPTS 3
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static int cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
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unsigned int size, struct snd_dma_buffer *dmab,
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int direction)
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{
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struct hdac_ext_stream *dsp_stream;
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struct hdac_stream *hstream;
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struct pci_dev *pci = to_pci_dev(sdev->dev);
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int ret;
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if (direction != SNDRV_PCM_STREAM_PLAYBACK) {
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dev_err(sdev->dev, "error: code loading DMA is playback only\n");
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return -EINVAL;
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}
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dsp_stream = hda_dsp_stream_get(sdev, direction);
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if (!dsp_stream) {
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dev_err(sdev->dev, "error: no stream available\n");
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return -ENODEV;
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}
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hstream = &dsp_stream->hstream;
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hstream->substream = NULL;
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/* allocate DMA buffer */
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ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
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if (ret < 0) {
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dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
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goto error;
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}
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hstream->period_bytes = 0;/* initialize period_bytes */
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hstream->format_val = format;
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hstream->bufsize = size;
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ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
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if (ret < 0) {
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dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
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goto error;
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}
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hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
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return hstream->stream_tag;
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error:
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hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
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snd_dma_free_pages(dmab);
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return ret;
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}
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/*
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* first boot sequence has some extra steps. core 0 waits for power
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* status on core 1, so power up core 1 also momentarily, keep it in
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* reset/stall and then turn it off
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*/
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static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata,
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u32 fwsize, int stream_tag)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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unsigned int status;
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int ret;
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int i;
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/* step 1: power up corex */
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ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
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goto err;
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}
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/* DSP is powered up, set all SSPs to slave mode */
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for (i = 0; i < chip->ssp_count; i++) {
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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chip->ssp_base_offset
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+ i * SSP_DEV_MEM_SIZE
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+ SSP_SSC1_OFFSET,
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SSP_SET_SLAVE,
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SSP_SET_SLAVE);
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}
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/* step 2: purge FW request */
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
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chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
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((stream_tag - 1) << 9)));
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/* step 3: unset core 0 reset state & unstall/run core 0 */
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ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core start failed %d\n", ret);
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ret = -EIO;
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goto err;
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}
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/* step 4: wait for IPC DONE bit from ROM */
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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chip->ipc_ack, status,
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((status & chip->ipc_ack_mask)
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== chip->ipc_ack_mask),
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_INIT_TIMEOUT_US);
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if (ret < 0) {
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dev_err(sdev->dev, "error: %s: timeout for HIPCIE done\n",
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__func__);
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goto err;
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}
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/* set DONE bit to clear the reply IPC message */
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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chip->ipc_ack,
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chip->ipc_ack_mask,
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chip->ipc_ack_mask);
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/* step 5: power down corex */
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ret = hda_dsp_core_power_down(sdev,
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chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core x power down failed\n");
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goto err;
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}
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/* step 6: enable IPC interrupts */
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hda_dsp_ipc_int_enable(sdev);
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/* step 7: wait for ROM init */
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_SRAM_REG_ROM_STATUS, status,
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((status & HDA_DSP_ROM_STS_MASK)
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== HDA_DSP_ROM_INIT),
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HDA_DSP_REG_POLL_INTERVAL_US,
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chip->rom_init_timeout *
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USEC_PER_MSEC);
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if (!ret)
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return 0;
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dev_err(sdev->dev,
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"error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
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__func__);
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err:
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hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
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hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
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return ret;
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}
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static int cl_trigger(struct snd_sof_dev *sdev,
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struct hdac_ext_stream *stream, int cmd)
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{
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struct hdac_stream *hstream = &stream->hstream;
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int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
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/* code loader is special case that reuses stream ops */
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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1 << hstream->index,
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1 << hstream->index);
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset,
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SOF_HDA_SD_CTL_DMA_START |
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SOF_HDA_CL_DMA_SD_INT_MASK,
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SOF_HDA_SD_CTL_DMA_START |
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SOF_HDA_CL_DMA_SD_INT_MASK);
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hstream->running = true;
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return 0;
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default:
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return hda_dsp_stream_trigger(sdev, stream, cmd);
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}
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}
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static struct hdac_ext_stream *get_stream_with_tag(struct snd_sof_dev *sdev,
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int tag)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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struct hdac_stream *s;
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/* get stream with tag */
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list_for_each_entry(s, &bus->stream_list, list) {
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if (s->direction == SNDRV_PCM_STREAM_PLAYBACK &&
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s->stream_tag == tag) {
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return stream_to_hdac_ext_stream(s);
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}
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}
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return NULL;
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}
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static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
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struct hdac_ext_stream *stream)
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{
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struct hdac_stream *hstream = &stream->hstream;
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int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
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int ret;
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ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
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hda_dsp_stream_put(sdev, SNDRV_PCM_STREAM_PLAYBACK,
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hstream->stream_tag);
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hstream->running = 0;
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hstream->substream = NULL;
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/* reset BDL address */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
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snd_dma_free_pages(dmab);
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dmab->area = NULL;
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hstream->bufsize = 0;
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hstream->format_val = 0;
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return ret;
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}
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static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
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{
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unsigned int reg;
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int ret, status;
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ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
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if (ret < 0) {
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dev_err(sdev->dev, "error: DMA trigger start failed\n");
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return ret;
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}
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status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
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HDA_DSP_SRAM_REG_ROM_STATUS, reg,
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((reg & HDA_DSP_ROM_STS_MASK)
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== HDA_DSP_ROM_FW_ENTERED),
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HDA_DSP_REG_POLL_INTERVAL_US,
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HDA_DSP_BASEFW_TIMEOUT_US);
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/*
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* even in case of errors we still need to stop the DMAs,
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* but we return the initial error should the DMA stop also fail
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*/
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if (status < 0) {
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dev_err(sdev->dev,
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"error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
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__func__);
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}
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ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
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if (ret < 0) {
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dev_err(sdev->dev, "error: DMA trigger stop failed\n");
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if (!status)
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status = ret;
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}
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return status;
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}
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int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
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{
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struct snd_sof_pdata *plat_data = sdev->pdata;
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const struct sof_dev_desc *desc = plat_data->desc;
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const struct sof_intel_dsp_desc *chip_info;
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struct hdac_ext_stream *stream;
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struct firmware stripped_firmware;
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int ret, ret1, tag, i;
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chip_info = desc->chip_info;
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if (plat_data->fw->size < plat_data->fw_offset) {
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dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
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return -EINVAL;
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}
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stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset;
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stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
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/* init for booting wait */
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init_waitqueue_head(&sdev->boot_wait);
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/* prepare DMA for code loader stream */
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tag = cl_stream_prepare(sdev, 0x40, stripped_firmware.size,
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&sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK);
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if (tag < 0) {
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dev_err(sdev->dev, "error: dma prepare for fw loading err: %x\n",
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tag);
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return tag;
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}
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/* get stream with tag */
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stream = get_stream_with_tag(sdev, tag);
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if (!stream) {
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dev_err(sdev->dev,
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"error: could not get stream with stream tag %d\n",
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tag);
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ret = -ENODEV;
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goto err;
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}
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memcpy(sdev->dmab.area, stripped_firmware.data,
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stripped_firmware.size);
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/* try ROM init a few times before giving up */
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for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
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ret = cl_dsp_init(sdev, stripped_firmware.data,
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stripped_firmware.size, tag);
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/* don't retry anymore if successful */
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if (!ret)
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break;
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dev_dbg(sdev->dev, "iteration %d of Core En/ROM load failed: %d\n",
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i, ret);
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dev_dbg(sdev->dev, "Error code=0x%x: FW status=0x%x\n",
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snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_SRAM_REG_ROM_ERROR),
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snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_SRAM_REG_ROM_STATUS));
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}
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if (i == HDA_FW_BOOT_ATTEMPTS) {
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dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
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i, ret);
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goto cleanup;
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}
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/*
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* When a SoundWire link is in clock stop state, a Slave
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* device may trigger in-band wakes for events such as jack
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* insertion or acoustic event detection. This event will lead
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* to a WAKEEN interrupt, handled by the PCI device and routed
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* to PME if the PCI device is in D3. The resume function in
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* audio PCI driver will be invoked by ACPI for PME event and
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* initialize the device and process WAKEEN interrupt.
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*
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* The WAKEEN interrupt should be processed ASAP to prevent an
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* interrupt flood, otherwise other interrupts, such IPC,
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* cannot work normally. The WAKEEN is handled after the ROM
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* is initialized successfully, which ensures power rails are
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* enabled before accessing the SoundWire SHIM registers
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*/
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if (!sdev->first_boot)
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hda_sdw_process_wakeen(sdev);
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/*
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* at this point DSP ROM has been initialized and
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* should be ready for code loading and firmware boot
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*/
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ret = cl_copy_fw(sdev, stream);
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if (!ret)
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dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
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else
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dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret);
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cleanup:
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/*
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* Perform codeloader stream cleanup.
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* This should be done even if firmware loading fails.
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* If the cleanup also fails, we return the initial error
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*/
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ret1 = cl_cleanup(sdev, &sdev->dmab, stream);
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if (ret1 < 0) {
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dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
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/* set return value to indicate cleanup failure */
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if (!ret)
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ret = ret1;
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}
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/*
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* return master core id if both fw copy
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* and stream clean up are successful
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*/
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if (!ret)
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return chip_info->init_core_mask;
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/* dump dsp registers and disable DSP upon error */
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err:
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hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
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/* disable DSP */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
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SOF_HDA_REG_PP_PPCTL,
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SOF_HDA_PPCTL_GPROCEN, 0);
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return ret;
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}
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/* pre fw run operations */
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int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
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{
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/* disable clock gating and power gating */
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return hda_dsp_ctrl_clock_power_gating(sdev, false);
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}
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/* post fw run operations */
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int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
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{
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int ret;
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if (sdev->first_boot) {
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ret = hda_sdw_startup(sdev);
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if (ret < 0) {
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dev_err(sdev->dev,
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"error: could not startup SoundWire links\n");
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return ret;
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}
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}
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hda_sdw_int_enable(sdev, true);
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/* re-enable clock gating and power gating */
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return hda_dsp_ctrl_clock_power_gating(sdev, true);
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}
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