425 lines
11 KiB
C
425 lines
11 KiB
C
/*
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* Palmchip bk3710 IDE controller
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/ide.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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/* Offset of the primary interface registers */
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#define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0
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/* Primary Control Offset */
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#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
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/*
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* PalmChip 3710 IDE Controller UDMA timing structure Definition
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*/
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struct palm_bk3710_udmatiming {
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unsigned int rptime; /* Ready to pause time */
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unsigned int cycletime; /* Cycle Time */
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};
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#define BK3710_BMICP 0x00
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#define BK3710_BMISP 0x02
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#define BK3710_BMIDTP 0x04
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#define BK3710_BMICS 0x08
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#define BK3710_BMISS 0x0A
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#define BK3710_BMIDTS 0x0C
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#define BK3710_IDETIMP 0x40
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#define BK3710_IDETIMS 0x42
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#define BK3710_SIDETIM 0x44
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#define BK3710_SLEWCTL 0x45
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#define BK3710_IDESTATUS 0x47
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#define BK3710_UDMACTL 0x48
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#define BK3710_UDMATIM 0x4A
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#define BK3710_MISCCTL 0x50
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#define BK3710_REGSTB 0x54
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#define BK3710_REGRCVR 0x58
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#define BK3710_DATSTB 0x5C
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#define BK3710_DATRCVR 0x60
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#define BK3710_DMASTB 0x64
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#define BK3710_DMARCVR 0x68
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#define BK3710_UDMASTB 0x6C
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#define BK3710_UDMATRP 0x70
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#define BK3710_UDMAENV 0x74
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#define BK3710_IORDYTMP 0x78
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#define BK3710_IORDYTMS 0x7C
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static unsigned ideclk_period; /* in nanoseconds */
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static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
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{160, 240}, /* UDMA Mode 0 */
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{125, 160}, /* UDMA Mode 1 */
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{100, 120}, /* UDMA Mode 2 */
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{100, 90}, /* UDMA Mode 3 */
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{100, 60}, /* UDMA Mode 4 */
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{85, 40}, /* UDMA Mode 5 */
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};
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static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,
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unsigned int mode)
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{
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u8 tenv, trp, t0;
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u32 val32;
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u16 val16;
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/* DMA Data Setup */
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t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime,
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ideclk_period) - 1;
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tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
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trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime,
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ideclk_period) - 1;
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/* udmatim Register */
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val16 = readw(base + BK3710_UDMATIM) & (dev ? 0xFF0F : 0xFFF0);
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val16 |= (mode << (dev ? 4 : 0));
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writew(val16, base + BK3710_UDMATIM);
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/* udmastb Ultra DMA Access Strobe Width */
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val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (t0 << (dev ? 8 : 0));
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writel(val32, base + BK3710_UDMASTB);
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/* udmatrp Ultra DMA Ready to Pause Time */
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val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
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val32 |= (trp << (dev ? 8 : 0));
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writel(val32, base + BK3710_UDMATRP);
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/* udmaenv Ultra DMA envelop Time */
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val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
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val32 |= (tenv << (dev ? 8 : 0));
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writel(val32, base + BK3710_UDMAENV);
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/* Enable UDMA for Device */
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val16 = readw(base + BK3710_UDMACTL) | (1 << dev);
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writew(val16, base + BK3710_UDMACTL);
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}
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static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev,
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unsigned short min_cycle,
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unsigned int mode)
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{
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u8 td, tkw, t0;
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u32 val32;
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u16 val16;
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struct ide_timing *t;
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int cycletime;
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t = ide_timing_find_mode(mode);
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cycletime = max_t(int, t->cycle, min_cycle);
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/* DMA Data Setup */
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t0 = DIV_ROUND_UP(cycletime, ideclk_period);
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td = DIV_ROUND_UP(t->active, ideclk_period);
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tkw = t0 - td - 1;
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td -= 1;
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val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (td << (dev ? 8 : 0));
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writel(val32, base + BK3710_DMASTB);
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val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
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val32 |= (tkw << (dev ? 8 : 0));
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writel(val32, base + BK3710_DMARCVR);
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/* Disable UDMA for Device */
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val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev);
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writew(val16, base + BK3710_UDMACTL);
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}
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static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate,
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unsigned int dev, unsigned int cycletime,
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unsigned int mode)
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{
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u8 t2, t2i, t0;
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u32 val32;
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struct ide_timing *t;
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/* PIO Data Setup */
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t0 = DIV_ROUND_UP(cycletime, ideclk_period);
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t2 = DIV_ROUND_UP(ide_timing_find_mode(XFER_PIO_0 + mode)->active,
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ideclk_period);
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t2i = t0 - t2 - 1;
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t2 -= 1;
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val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (t2 << (dev ? 8 : 0));
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writel(val32, base + BK3710_DATSTB);
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val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
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val32 |= (t2i << (dev ? 8 : 0));
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writel(val32, base + BK3710_DATRCVR);
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if (mate) {
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u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);
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if (mode2 < mode)
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mode = mode2;
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}
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/* TASKFILE Setup */
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t = ide_timing_find_mode(XFER_PIO_0 + mode);
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t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
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t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
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t2i = t0 - t2 - 1;
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t2 -= 1;
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val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
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val32 |= (t2 << (dev ? 8 : 0));
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writel(val32, base + BK3710_REGSTB);
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val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
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val32 |= (t2i << (dev ? 8 : 0));
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writel(val32, base + BK3710_REGRCVR);
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}
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static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
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{
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int is_slave = drive->dn & 1;
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void __iomem *base = (void *)drive->hwif->dma_base;
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if (xferspeed >= XFER_UDMA_0) {
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palm_bk3710_setudmamode(base, is_slave,
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xferspeed - XFER_UDMA_0);
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} else {
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palm_bk3710_setdmamode(base, is_slave,
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drive->id[ATA_ID_EIDE_DMA_MIN],
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xferspeed);
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}
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}
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static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
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{
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unsigned int cycle_time;
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int is_slave = drive->dn & 1;
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ide_drive_t *mate;
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void __iomem *base = (void *)drive->hwif->dma_base;
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/*
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* Obtain the drive PIO data for tuning the Palm Chip registers
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*/
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cycle_time = ide_pio_cycle_time(drive, pio);
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mate = ide_get_pair_dev(drive);
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palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
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}
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static void __devinit palm_bk3710_chipinit(void __iomem *base)
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{
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/*
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* enable the reset_en of ATA controller so that when ata signals
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* are brought out, by writing into device config. at that
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* time por_n signal should not be 'Z' and have a stable value.
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*/
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writel(0x0300, base + BK3710_MISCCTL);
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/* wait for some time and deassert the reset of ATA Device. */
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mdelay(100);
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/* Deassert the Reset */
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writel(0x0200, base + BK3710_MISCCTL);
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/*
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* Program the IDETIMP Register Value based on the following assumptions
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*
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* (ATA_IDETIMP_IDEEN , ENABLE ) |
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* (ATA_IDETIMP_SLVTIMEN , DISABLE) |
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* (ATA_IDETIMP_RDYSMPL , 70NS) |
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* (ATA_IDETIMP_RDYRCVRY , 50NS) |
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* (ATA_IDETIMP_DMAFTIM1 , PIOCOMP) |
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* (ATA_IDETIMP_PREPOST1 , DISABLE) |
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* (ATA_IDETIMP_RDYSEN1 , DISABLE) |
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* (ATA_IDETIMP_PIOFTIM1 , DISABLE) |
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* (ATA_IDETIMP_DMAFTIM0 , PIOCOMP) |
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* (ATA_IDETIMP_PREPOST0 , DISABLE) |
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* (ATA_IDETIMP_RDYSEN0 , DISABLE) |
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* (ATA_IDETIMP_PIOFTIM0 , DISABLE)
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*/
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writew(0xB388, base + BK3710_IDETIMP);
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/*
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* Configure SIDETIM Register
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* (ATA_SIDETIM_RDYSMPS1 ,120NS ) |
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* (ATA_SIDETIM_RDYRCYS1 ,120NS )
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*/
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writeb(0, base + BK3710_SIDETIM);
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/*
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* UDMACTL Ultra-ATA DMA Control
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* (ATA_UDMACTL_UDMAP1 , 0 ) |
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* (ATA_UDMACTL_UDMAP0 , 0 )
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*
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*/
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writew(0, base + BK3710_UDMACTL);
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/*
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* MISCCTL Miscellaneous Conrol Register
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* (ATA_MISCCTL_RSTMODEP , 1) |
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* (ATA_MISCCTL_RESETP , 0) |
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* (ATA_MISCCTL_TIMORIDE , 1)
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*/
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writel(0x201, base + BK3710_MISCCTL);
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/*
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* IORDYTMP IORDY Timer for Primary Register
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* (ATA_IORDYTMP_IORDYTMP , 0xffff )
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*/
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writel(0xFFFF, base + BK3710_IORDYTMP);
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/*
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* Configure BMISP Register
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* (ATA_BMISP_DMAEN1 , DISABLE ) |
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* (ATA_BMISP_DMAEN0 , DISABLE ) |
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* (ATA_BMISP_IORDYINT , CLEAR) |
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* (ATA_BMISP_INTRSTAT , CLEAR) |
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* (ATA_BMISP_DMAERROR , CLEAR)
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*/
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writew(0, base + BK3710_BMISP);
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palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
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palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
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}
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static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif)
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{
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return ATA_CBL_PATA80;
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}
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static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif,
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const struct ide_port_info *d)
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{
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printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
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if (ide_allocate_dma_engine(hwif))
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return -1;
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hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
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hwif->dma_ops = &sff_dma_ops;
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return 0;
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}
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static const struct ide_port_ops palm_bk3710_ports_ops = {
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.set_pio_mode = palm_bk3710_set_pio_mode,
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.set_dma_mode = palm_bk3710_set_dma_mode,
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.cable_detect = palm_bk3710_cable_detect,
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};
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static struct ide_port_info __devinitdata palm_bk3710_port_info = {
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.init_dma = palm_bk3710_init_dma,
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.port_ops = &palm_bk3710_ports_ops,
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.host_flags = IDE_HFLAG_MMIO,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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};
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static int __init palm_bk3710_probe(struct platform_device *pdev)
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{
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struct clk *clk;
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struct resource *mem, *irq;
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unsigned long base, rate;
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int i, rc;
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hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
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clk = clk_get(&pdev->dev, "IDECLK");
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if (IS_ERR(clk))
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return -ENODEV;
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clk_enable(clk);
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rate = clk_get_rate(clk);
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ideclk_period = 1000000000UL / rate;
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/* Register the IDE interface with Linux ATA Interface */
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memset(&hw, 0, sizeof(hw));
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (mem == NULL) {
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printk(KERN_ERR "failed to get memory region resource\n");
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return -ENODEV;
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}
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (irq == NULL) {
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printk(KERN_ERR "failed to get IRQ resource\n");
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return -ENODEV;
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}
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if (request_mem_region(mem->start, mem->end - mem->start + 1,
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"palm_bk3710") == NULL) {
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printk(KERN_ERR "failed to request memory region\n");
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return -EBUSY;
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}
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base = IO_ADDRESS(mem->start);
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/* Configure the Palm Chip controller */
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palm_bk3710_chipinit((void __iomem *)base);
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for (i = 0; i < IDE_NR_PORTS - 2; i++)
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hw.io_ports_array[i] = base + IDE_PALM_ATA_PRI_REG_OFFSET + i;
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hw.io_ports.ctl_addr = base + IDE_PALM_ATA_PRI_CTL_OFFSET;
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hw.irq = irq->start;
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hw.dev = &pdev->dev;
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hw.chipset = ide_palm3710;
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palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 :
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ATA_UDMA5;
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rc = ide_host_add(&palm_bk3710_port_info, hws, NULL);
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if (rc)
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goto out;
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return 0;
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out:
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printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n");
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return rc;
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}
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/* work with hotplug and coldplug */
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MODULE_ALIAS("platform:palm_bk3710");
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static struct platform_driver platform_bk_driver = {
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.driver = {
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.name = "palm_bk3710",
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.owner = THIS_MODULE,
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},
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};
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static int __init palm_bk3710_init(void)
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{
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return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe);
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}
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module_init(palm_bk3710_init);
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MODULE_LICENSE("GPL");
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