267 lines
7.2 KiB
C
267 lines
7.2 KiB
C
/*
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* linux/arch/parisc/kernel/time.c
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*
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* Copyright (C) 1991, 1992, 1995 Linus Torvalds
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* Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
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* Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
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*
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* 1994-07-02 Alan Modra
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* fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
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* 1998-12-20 Updated NTP code according to technical memorandum Jan '96
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* "A Kernel Model for Precision Timekeeping" by Dave Mills
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*/
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/profile.h>
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#include <linux/clocksource.h>
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#include <linux/platform_device.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/param.h>
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#include <asm/pdc.h>
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#include <asm/led.h>
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#include <linux/timex.h>
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static unsigned long clocktick __read_mostly; /* timer cycles per tick */
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/*
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* We keep time on PA-RISC Linux by using the Interval Timer which is
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* a pair of registers; one is read-only and one is write-only; both
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* accessed through CR16. The read-only register is 32 or 64 bits wide,
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* and increments by 1 every CPU clock tick. The architecture only
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* guarantees us a rate between 0.5 and 2, but all implementations use a
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* rate of 1. The write-only register is 32-bits wide. When the lowest
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* 32 bits of the read-only register compare equal to the write-only
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* register, it raises a maskable external interrupt. Each processor has
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* an Interval Timer of its own and they are not synchronised.
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*
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* We want to generate an interrupt every 1/HZ seconds. So we program
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* CR16 to interrupt every @clocktick cycles. The it_value in cpu_data
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* is programmed with the intended time of the next tick. We can be
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* held off for an arbitrarily long period of time by interrupts being
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* disabled, so we may miss one or more ticks.
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*/
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irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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unsigned long now;
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unsigned long next_tick;
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unsigned long cycles_elapsed, ticks_elapsed;
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unsigned long cycles_remainder;
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unsigned int cpu = smp_processor_id();
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struct cpuinfo_parisc *cpuinfo = &cpu_data[cpu];
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/* gcc can optimize for "read-only" case with a local clocktick */
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unsigned long cpt = clocktick;
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profile_tick(CPU_PROFILING);
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/* Initialize next_tick to the expected tick time. */
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next_tick = cpuinfo->it_value;
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/* Get current interval timer.
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* CR16 reads as 64 bits in CPU wide mode.
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* CR16 reads as 32 bits in CPU narrow mode.
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*/
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now = mfctl(16);
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cycles_elapsed = now - next_tick;
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if ((cycles_elapsed >> 5) < cpt) {
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/* use "cheap" math (add/subtract) instead
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* of the more expensive div/mul method
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*/
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cycles_remainder = cycles_elapsed;
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ticks_elapsed = 1;
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while (cycles_remainder > cpt) {
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cycles_remainder -= cpt;
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ticks_elapsed++;
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}
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} else {
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cycles_remainder = cycles_elapsed % cpt;
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ticks_elapsed = 1 + cycles_elapsed / cpt;
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}
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/* Can we differentiate between "early CR16" (aka Scenario 1) and
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* "long delay" (aka Scenario 3)? I don't think so.
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*
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* We expected timer_interrupt to be delivered at least a few hundred
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* cycles after the IT fires. But it's arbitrary how much time passes
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* before we call it "late". I've picked one second.
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*/
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if (unlikely(ticks_elapsed > HZ)) {
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/* Scenario 3: very long delay? bad in any case */
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printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!"
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" cycles %lX rem %lX "
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" next/now %lX/%lX\n",
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cpu,
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cycles_elapsed, cycles_remainder,
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next_tick, now );
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}
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/* convert from "division remainder" to "remainder of clock tick" */
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cycles_remainder = cpt - cycles_remainder;
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/* Determine when (in CR16 cycles) next IT interrupt will fire.
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* We want IT to fire modulo clocktick even if we miss/skip some.
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* But those interrupts don't in fact get delivered that regularly.
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*/
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next_tick = now + cycles_remainder;
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cpuinfo->it_value = next_tick;
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/* Skip one clocktick on purpose if we are likely to miss next_tick.
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* We want to avoid the new next_tick being less than CR16.
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* If that happened, itimer wouldn't fire until CR16 wrapped.
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* We'll catch the tick we missed on the tick after that.
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*/
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if (!(cycles_remainder >> 13))
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next_tick += cpt;
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/* Program the IT when to deliver the next interrupt. */
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/* Only bottom 32-bits of next_tick are written to cr16. */
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mtctl(next_tick, 16);
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/* Done mucking with unreliable delivery of interrupts.
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* Go do system house keeping.
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*/
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if (!--cpuinfo->prof_counter) {
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cpuinfo->prof_counter = cpuinfo->prof_multiplier;
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update_process_times(user_mode(get_irq_regs()));
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}
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if (cpu == 0) {
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write_seqlock(&xtime_lock);
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do_timer(ticks_elapsed);
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write_sequnlock(&xtime_lock);
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}
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return IRQ_HANDLED;
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}
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unsigned long profile_pc(struct pt_regs *regs)
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{
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unsigned long pc = instruction_pointer(regs);
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if (regs->gr[0] & PSW_N)
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pc -= 4;
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#ifdef CONFIG_SMP
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if (in_lock_functions(pc))
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pc = regs->gr[2];
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#endif
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return pc;
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}
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EXPORT_SYMBOL(profile_pc);
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/* clock source code */
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static cycle_t read_cr16(void)
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{
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return get_cycles();
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}
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static struct clocksource clocksource_cr16 = {
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.name = "cr16",
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.rating = 300,
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.read = read_cr16,
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.mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
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.mult = 0, /* to be set */
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.shift = 22,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#ifdef CONFIG_SMP
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int update_cr16_clocksource(void)
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{
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/* since the cr16 cycle counters are not synchronized across CPUs,
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we'll check if we should switch to a safe clocksource: */
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if (clocksource_cr16.rating != 0 && num_online_cpus() > 1) {
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clocksource_change_rating(&clocksource_cr16, 0);
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return 1;
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}
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return 0;
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}
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#else
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int update_cr16_clocksource(void)
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{
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return 0; /* no change */
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}
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#endif /*CONFIG_SMP*/
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void __init start_cpu_itimer(void)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long next_tick = mfctl(16) + clocktick;
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mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
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cpu_data[cpu].it_value = next_tick;
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}
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struct platform_device rtc_parisc_dev = {
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.name = "rtc-parisc",
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.id = -1,
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};
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static int __init rtc_init(void)
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{
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int ret;
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ret = platform_device_register(&rtc_parisc_dev);
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if (ret < 0)
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printk(KERN_ERR "unable to register rtc device...\n");
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/* not necessarily an error */
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return 0;
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}
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module_init(rtc_init);
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void __init time_init(void)
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{
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static struct pdc_tod tod_data;
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unsigned long current_cr16_khz;
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clocktick = (100 * PAGE0->mem_10msec) / HZ;
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start_cpu_itimer(); /* get CPU 0 started */
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/* register at clocksource framework */
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current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */
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clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz,
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clocksource_cr16.shift);
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clocksource_register(&clocksource_cr16);
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if (pdc_tod_read(&tod_data) == 0) {
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unsigned long flags;
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write_seqlock_irqsave(&xtime_lock, flags);
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xtime.tv_sec = tod_data.tod_sec;
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xtime.tv_nsec = tod_data.tod_usec * 1000;
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set_normalized_timespec(&wall_to_monotonic,
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-xtime.tv_sec, -xtime.tv_nsec);
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write_sequnlock_irqrestore(&xtime_lock, flags);
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} else {
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printk(KERN_ERR "Error reading tod clock\n");
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xtime.tv_sec = 0;
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xtime.tv_nsec = 0;
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}
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}
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