538 lines
14 KiB
C
538 lines
14 KiB
C
/*
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* Copyright (C) 1991, 1992 Linus Torvalds
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* Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
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* Copyright (C) 2011 Don Zickus Red Hat, Inc.
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*
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* Pentium III FXSR, SSE support
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* Gareth Hughes <gareth@valinux.com>, May 2000
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*/
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/*
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* Handle hardware traps and faults.
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*/
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#include <linux/spinlock.h>
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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#include <linux/nmi.h>
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#include <linux/delay.h>
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#include <linux/hardirq.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/mca.h>
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#if defined(CONFIG_EDAC)
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#include <linux/edac.h>
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#endif
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#include <linux/atomic.h>
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#include <asm/traps.h>
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#include <asm/mach_traps.h>
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#include <asm/nmi.h>
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#include <asm/x86_init.h>
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#define NMI_MAX_NAMELEN 16
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struct nmiaction {
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struct list_head list;
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nmi_handler_t handler;
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unsigned int flags;
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char *name;
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};
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struct nmi_desc {
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spinlock_t lock;
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struct list_head head;
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};
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static struct nmi_desc nmi_desc[NMI_MAX] =
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{
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{
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.lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock),
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.head = LIST_HEAD_INIT(nmi_desc[0].head),
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},
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{
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.lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
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.head = LIST_HEAD_INIT(nmi_desc[1].head),
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},
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};
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struct nmi_stats {
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unsigned int normal;
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unsigned int unknown;
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unsigned int external;
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unsigned int swallow;
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};
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static DEFINE_PER_CPU(struct nmi_stats, nmi_stats);
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static int ignore_nmis;
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int unknown_nmi_panic;
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/*
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* Prevent NMI reason port (0x61) being accessed simultaneously, can
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* only be used in NMI handler.
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*/
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static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
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static int __init setup_unknown_nmi_panic(char *str)
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{
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unknown_nmi_panic = 1;
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return 1;
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}
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__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
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#define nmi_to_desc(type) (&nmi_desc[type])
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static int notrace __kprobes nmi_handle(unsigned int type, struct pt_regs *regs, bool b2b)
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{
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struct nmi_desc *desc = nmi_to_desc(type);
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struct nmiaction *a;
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int handled=0;
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rcu_read_lock();
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/*
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* NMIs are edge-triggered, which means if you have enough
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* of them concurrently, you can lose some because only one
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* can be latched at any given time. Walk the whole list
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* to handle those situations.
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*/
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list_for_each_entry_rcu(a, &desc->head, list)
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handled += a->handler(type, regs);
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rcu_read_unlock();
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/* return total number of NMI events handled */
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return handled;
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}
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static int __setup_nmi(unsigned int type, struct nmiaction *action)
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{
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struct nmi_desc *desc = nmi_to_desc(type);
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unsigned long flags;
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spin_lock_irqsave(&desc->lock, flags);
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/*
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* most handlers of type NMI_UNKNOWN never return because
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* they just assume the NMI is theirs. Just a sanity check
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* to manage expectations
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*/
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WARN_ON_ONCE(type == NMI_UNKNOWN && !list_empty(&desc->head));
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/*
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* some handlers need to be executed first otherwise a fake
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* event confuses some handlers (kdump uses this flag)
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*/
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if (action->flags & NMI_FLAG_FIRST)
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list_add_rcu(&action->list, &desc->head);
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else
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list_add_tail_rcu(&action->list, &desc->head);
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spin_unlock_irqrestore(&desc->lock, flags);
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return 0;
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}
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static struct nmiaction *__free_nmi(unsigned int type, const char *name)
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{
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struct nmi_desc *desc = nmi_to_desc(type);
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struct nmiaction *n;
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unsigned long flags;
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spin_lock_irqsave(&desc->lock, flags);
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list_for_each_entry_rcu(n, &desc->head, list) {
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/*
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* the name passed in to describe the nmi handler
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* is used as the lookup key
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*/
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if (!strcmp(n->name, name)) {
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WARN(in_nmi(),
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"Trying to free NMI (%s) from NMI context!\n", n->name);
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list_del_rcu(&n->list);
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break;
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}
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}
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spin_unlock_irqrestore(&desc->lock, flags);
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synchronize_rcu();
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return (n);
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}
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int register_nmi_handler(unsigned int type, nmi_handler_t handler,
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unsigned long nmiflags, const char *devname)
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{
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struct nmiaction *action;
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int retval = -ENOMEM;
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if (!handler)
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return -EINVAL;
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action = kzalloc(sizeof(struct nmiaction), GFP_KERNEL);
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if (!action)
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goto fail_action;
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action->handler = handler;
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action->flags = nmiflags;
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action->name = kstrndup(devname, NMI_MAX_NAMELEN, GFP_KERNEL);
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if (!action->name)
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goto fail_action_name;
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retval = __setup_nmi(type, action);
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if (retval)
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goto fail_setup_nmi;
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return retval;
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fail_setup_nmi:
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kfree(action->name);
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fail_action_name:
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kfree(action);
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fail_action:
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return retval;
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}
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EXPORT_SYMBOL_GPL(register_nmi_handler);
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void unregister_nmi_handler(unsigned int type, const char *name)
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{
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struct nmiaction *a;
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a = __free_nmi(type, name);
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if (a) {
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kfree(a->name);
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kfree(a);
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}
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}
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EXPORT_SYMBOL_GPL(unregister_nmi_handler);
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static notrace __kprobes void
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pci_serr_error(unsigned char reason, struct pt_regs *regs)
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{
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pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
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reason, smp_processor_id());
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/*
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* On some machines, PCI SERR line is used to report memory
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* errors. EDAC makes use of it.
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*/
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#if defined(CONFIG_EDAC)
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if (edac_handler_set()) {
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edac_atomic_assert_error();
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return;
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}
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#endif
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if (panic_on_unrecovered_nmi)
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panic("NMI: Not continuing");
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pr_emerg("Dazed and confused, but trying to continue\n");
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/* Clear and disable the PCI SERR error line. */
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reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
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outb(reason, NMI_REASON_PORT);
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}
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static notrace __kprobes void
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io_check_error(unsigned char reason, struct pt_regs *regs)
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{
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unsigned long i;
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pr_emerg(
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"NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
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reason, smp_processor_id());
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show_registers(regs);
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if (panic_on_io_nmi)
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panic("NMI IOCK error: Not continuing");
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/* Re-enable the IOCK line, wait for a few seconds */
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reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
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outb(reason, NMI_REASON_PORT);
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i = 20000;
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while (--i) {
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touch_nmi_watchdog();
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udelay(100);
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}
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reason &= ~NMI_REASON_CLEAR_IOCHK;
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outb(reason, NMI_REASON_PORT);
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}
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static notrace __kprobes void
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unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
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{
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int handled;
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/*
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* Use 'false' as back-to-back NMIs are dealt with one level up.
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* Of course this makes having multiple 'unknown' handlers useless
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* as only the first one is ever run (unless it can actually determine
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* if it caused the NMI)
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*/
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handled = nmi_handle(NMI_UNKNOWN, regs, false);
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if (handled) {
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__this_cpu_add(nmi_stats.unknown, handled);
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return;
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}
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__this_cpu_add(nmi_stats.unknown, 1);
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#ifdef CONFIG_MCA
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/*
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* Might actually be able to figure out what the guilty party
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* is:
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*/
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if (MCA_bus) {
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mca_handle_nmi();
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return;
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}
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#endif
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pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
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reason, smp_processor_id());
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pr_emerg("Do you have a strange power saving mode enabled?\n");
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if (unknown_nmi_panic || panic_on_unrecovered_nmi)
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panic("NMI: Not continuing");
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pr_emerg("Dazed and confused, but trying to continue\n");
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}
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static DEFINE_PER_CPU(bool, swallow_nmi);
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static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
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static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
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{
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unsigned char reason = 0;
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int handled;
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bool b2b = false;
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/*
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* CPU-specific NMI must be processed before non-CPU-specific
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* NMI, otherwise we may lose it, because the CPU-specific
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* NMI can not be detected/processed on other CPUs.
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*/
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/*
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* Back-to-back NMIs are interesting because they can either
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* be two NMI or more than two NMIs (any thing over two is dropped
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* due to NMI being edge-triggered). If this is the second half
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* of the back-to-back NMI, assume we dropped things and process
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* more handlers. Otherwise reset the 'swallow' NMI behaviour
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*/
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if (regs->ip == __this_cpu_read(last_nmi_rip))
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b2b = true;
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else
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__this_cpu_write(swallow_nmi, false);
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__this_cpu_write(last_nmi_rip, regs->ip);
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handled = nmi_handle(NMI_LOCAL, regs, b2b);
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__this_cpu_add(nmi_stats.normal, handled);
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if (handled) {
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/*
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* There are cases when a NMI handler handles multiple
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* events in the current NMI. One of these events may
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* be queued for in the next NMI. Because the event is
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* already handled, the next NMI will result in an unknown
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* NMI. Instead lets flag this for a potential NMI to
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* swallow.
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*/
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if (handled > 1)
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__this_cpu_write(swallow_nmi, true);
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return;
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}
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/* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
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raw_spin_lock(&nmi_reason_lock);
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reason = x86_platform.get_nmi_reason();
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if (reason & NMI_REASON_MASK) {
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if (reason & NMI_REASON_SERR)
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pci_serr_error(reason, regs);
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else if (reason & NMI_REASON_IOCHK)
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io_check_error(reason, regs);
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#ifdef CONFIG_X86_32
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/*
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* Reassert NMI in case it became active
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* meanwhile as it's edge-triggered:
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*/
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reassert_nmi();
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#endif
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__this_cpu_add(nmi_stats.external, 1);
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raw_spin_unlock(&nmi_reason_lock);
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return;
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}
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raw_spin_unlock(&nmi_reason_lock);
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/*
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* Only one NMI can be latched at a time. To handle
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* this we may process multiple nmi handlers at once to
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* cover the case where an NMI is dropped. The downside
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* to this approach is we may process an NMI prematurely,
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* while its real NMI is sitting latched. This will cause
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* an unknown NMI on the next run of the NMI processing.
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*
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* We tried to flag that condition above, by setting the
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* swallow_nmi flag when we process more than one event.
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* This condition is also only present on the second half
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* of a back-to-back NMI, so we flag that condition too.
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*
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* If both are true, we assume we already processed this
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* NMI previously and we swallow it. Otherwise we reset
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* the logic.
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*
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* There are scenarios where we may accidentally swallow
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* a 'real' unknown NMI. For example, while processing
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* a perf NMI another perf NMI comes in along with a
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* 'real' unknown NMI. These two NMIs get combined into
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* one (as descibed above). When the next NMI gets
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* processed, it will be flagged by perf as handled, but
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* noone will know that there was a 'real' unknown NMI sent
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* also. As a result it gets swallowed. Or if the first
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* perf NMI returns two events handled then the second
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* NMI will get eaten by the logic below, again losing a
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* 'real' unknown NMI. But this is the best we can do
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* for now.
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*/
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if (b2b && __this_cpu_read(swallow_nmi))
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__this_cpu_add(nmi_stats.swallow, 1);
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else
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unknown_nmi_error(reason, regs);
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}
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/*
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* NMIs can hit breakpoints which will cause it to lose its
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* NMI context with the CPU when the breakpoint does an iret.
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*/
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#ifdef CONFIG_X86_32
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/*
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* For i386, NMIs use the same stack as the kernel, and we can
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* add a workaround to the iret problem in C. Simply have 3 states
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* the NMI can be in.
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*
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* 1) not running
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* 2) executing
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* 3) latched
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*
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* When no NMI is in progress, it is in the "not running" state.
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* When an NMI comes in, it goes into the "executing" state.
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* Normally, if another NMI is triggered, it does not interrupt
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* the running NMI and the HW will simply latch it so that when
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* the first NMI finishes, it will restart the second NMI.
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* (Note, the latch is binary, thus multiple NMIs triggering,
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* when one is running, are ignored. Only one NMI is restarted.)
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*
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* If an NMI hits a breakpoint that executes an iret, another
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* NMI can preempt it. We do not want to allow this new NMI
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* to run, but we want to execute it when the first one finishes.
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* We set the state to "latched", and the first NMI will perform
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* an cmpxchg on the state, and if it doesn't successfully
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* reset the state to "not running" it will restart the next
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* NMI.
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*/
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enum nmi_states {
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NMI_NOT_RUNNING,
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NMI_EXECUTING,
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NMI_LATCHED,
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};
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static DEFINE_PER_CPU(enum nmi_states, nmi_state);
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#define nmi_nesting_preprocess(regs) \
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do { \
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if (__get_cpu_var(nmi_state) != NMI_NOT_RUNNING) { \
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__get_cpu_var(nmi_state) = NMI_LATCHED; \
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return; \
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} \
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nmi_restart: \
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__get_cpu_var(nmi_state) = NMI_EXECUTING; \
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} while (0)
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#define nmi_nesting_postprocess() \
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do { \
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if (cmpxchg(&__get_cpu_var(nmi_state), \
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NMI_EXECUTING, NMI_NOT_RUNNING) != NMI_EXECUTING) \
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goto nmi_restart; \
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} while (0)
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#else /* x86_64 */
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/*
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* In x86_64 things are a bit more difficult. This has the same problem
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* where an NMI hitting a breakpoint that calls iret will remove the
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* NMI context, allowing a nested NMI to enter. What makes this more
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* difficult is that both NMIs and breakpoints have their own stack.
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* When a new NMI or breakpoint is executed, the stack is set to a fixed
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* point. If an NMI is nested, it will have its stack set at that same
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* fixed address that the first NMI had, and will start corrupting the
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* stack. This is handled in entry_64.S, but the same problem exists with
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* the breakpoint stack.
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*
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* If a breakpoint is being processed, and the debug stack is being used,
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* if an NMI comes in and also hits a breakpoint, the stack pointer
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* will be set to the same fixed address as the breakpoint that was
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* interrupted, causing that stack to be corrupted. To handle this case,
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* check if the stack that was interrupted is the debug stack, and if
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* so, change the IDT so that new breakpoints will use the current stack
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* and not switch to the fixed address. On return of the NMI, switch back
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* to the original IDT.
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*/
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static DEFINE_PER_CPU(int, update_debug_stack);
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static inline void nmi_nesting_preprocess(struct pt_regs *regs)
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{
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/*
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* If we interrupted a breakpoint, it is possible that
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* the nmi handler will have breakpoints too. We need to
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* change the IDT such that breakpoints that happen here
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* continue to use the NMI stack.
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*/
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if (unlikely(is_debug_stack(regs->sp))) {
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debug_stack_set_zero();
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__get_cpu_var(update_debug_stack) = 1;
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}
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}
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static inline void nmi_nesting_postprocess(void)
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{
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if (unlikely(__get_cpu_var(update_debug_stack)))
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debug_stack_reset();
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}
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#endif
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dotraplinkage notrace __kprobes void
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do_nmi(struct pt_regs *regs, long error_code)
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{
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nmi_nesting_preprocess(regs);
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nmi_enter();
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inc_irq_stat(__nmi_count);
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if (!ignore_nmis)
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default_do_nmi(regs);
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nmi_exit();
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/* On i386, may loop back to preprocess */
|
|
nmi_nesting_postprocess();
|
|
}
|
|
|
|
void stop_nmi(void)
|
|
{
|
|
ignore_nmis++;
|
|
}
|
|
|
|
void restart_nmi(void)
|
|
{
|
|
ignore_nmis--;
|
|
}
|
|
|
|
/* reset the back-to-back NMI logic */
|
|
void local_touch_nmi(void)
|
|
{
|
|
__this_cpu_write(last_nmi_rip, 0);
|
|
}
|