335 lines
8.8 KiB
C
335 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Aspeed AST2400/2500 ADC
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*
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* Copyright (C) 2017 Google, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/driver.h>
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#include <linux/iopoll.h>
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#define ASPEED_RESOLUTION_BITS 10
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#define ASPEED_CLOCKS_PER_SAMPLE 12
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#define ASPEED_REG_ENGINE_CONTROL 0x00
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#define ASPEED_REG_INTERRUPT_CONTROL 0x04
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#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
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#define ASPEED_REG_CLOCK_CONTROL 0x0C
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#define ASPEED_REG_MAX 0xC0
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#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
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#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
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#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
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#define ASPEED_ENGINE_ENABLE BIT(0)
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#define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
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#define ASPEED_ADC_INIT_POLLING_TIME 500
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#define ASPEED_ADC_INIT_TIMEOUT 500000
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struct aspeed_adc_model_data {
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const char *model_name;
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unsigned int min_sampling_rate; // Hz
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unsigned int max_sampling_rate; // Hz
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unsigned int vref_voltage; // mV
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bool wait_init_sequence;
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};
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struct aspeed_adc_data {
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struct device *dev;
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void __iomem *base;
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spinlock_t clk_lock;
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struct clk_hw *clk_prescaler;
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struct clk_hw *clk_scaler;
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struct reset_control *rst;
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};
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#define ASPEED_CHAN(_idx, _data_reg_addr) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (_idx), \
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.address = (_data_reg_addr), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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}
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static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
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ASPEED_CHAN(0, 0x10),
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ASPEED_CHAN(1, 0x12),
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ASPEED_CHAN(2, 0x14),
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ASPEED_CHAN(3, 0x16),
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ASPEED_CHAN(4, 0x18),
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ASPEED_CHAN(5, 0x1A),
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ASPEED_CHAN(6, 0x1C),
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ASPEED_CHAN(7, 0x1E),
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ASPEED_CHAN(8, 0x20),
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ASPEED_CHAN(9, 0x22),
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ASPEED_CHAN(10, 0x24),
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ASPEED_CHAN(11, 0x26),
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ASPEED_CHAN(12, 0x28),
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ASPEED_CHAN(13, 0x2A),
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ASPEED_CHAN(14, 0x2C),
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ASPEED_CHAN(15, 0x2E),
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};
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static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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const struct aspeed_adc_model_data *model_data =
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of_device_get_match_data(data->dev);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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*val = readw(data->base + chan->address);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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*val = model_data->vref_voltage;
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*val2 = ASPEED_RESOLUTION_BITS;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_SAMP_FREQ:
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*val = clk_get_rate(data->clk_scaler->clk) /
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ASPEED_CLOCKS_PER_SAMPLE;
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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const struct aspeed_adc_model_data *model_data =
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of_device_get_match_data(data->dev);
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switch (mask) {
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case IIO_CHAN_INFO_SAMP_FREQ:
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if (val < model_data->min_sampling_rate ||
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val > model_data->max_sampling_rate)
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return -EINVAL;
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clk_set_rate(data->clk_scaler->clk,
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val * ASPEED_CLOCKS_PER_SAMPLE);
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return 0;
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case IIO_CHAN_INFO_SCALE:
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case IIO_CHAN_INFO_RAW:
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/*
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* Technically, these could be written but the only reasons
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* for doing so seem better handled in userspace. EPERM is
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* returned to signal this is a policy choice rather than a
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* hardware limitation.
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*/
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return -EPERM;
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default:
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return -EINVAL;
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}
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}
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static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
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unsigned int reg, unsigned int writeval,
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unsigned int *readval)
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{
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
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return -EINVAL;
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*readval = readl(data->base + reg);
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return 0;
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}
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static const struct iio_info aspeed_adc_iio_info = {
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.read_raw = aspeed_adc_read_raw,
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.write_raw = aspeed_adc_write_raw,
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.debugfs_reg_access = aspeed_adc_reg_access,
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};
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static int aspeed_adc_probe(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev;
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struct aspeed_adc_data *data;
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const struct aspeed_adc_model_data *model_data;
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struct resource *res;
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const char *clk_parent_name;
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int ret;
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u32 adc_engine_control_reg_val;
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
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if (!indio_dev)
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return -ENOMEM;
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data = iio_priv(indio_dev);
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data->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->base))
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return PTR_ERR(data->base);
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/* Register ADC clock prescaler with source specified by device tree. */
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spin_lock_init(&data->clk_lock);
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clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
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data->clk_prescaler = clk_hw_register_divider(
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&pdev->dev, "prescaler", clk_parent_name, 0,
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data->base + ASPEED_REG_CLOCK_CONTROL,
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17, 15, 0, &data->clk_lock);
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if (IS_ERR(data->clk_prescaler))
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return PTR_ERR(data->clk_prescaler);
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/*
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* Register ADC clock scaler downstream from the prescaler. Allow rate
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* setting to adjust the prescaler as well.
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*/
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data->clk_scaler = clk_hw_register_divider(
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&pdev->dev, "scaler", "prescaler",
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CLK_SET_RATE_PARENT,
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data->base + ASPEED_REG_CLOCK_CONTROL,
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0, 10, 0, &data->clk_lock);
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if (IS_ERR(data->clk_scaler)) {
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ret = PTR_ERR(data->clk_scaler);
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goto scaler_error;
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}
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data->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(data->rst)) {
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dev_err(&pdev->dev,
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"invalid or missing reset controller device tree entry");
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ret = PTR_ERR(data->rst);
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goto reset_error;
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}
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reset_control_deassert(data->rst);
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model_data = of_device_get_match_data(&pdev->dev);
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if (model_data->wait_init_sequence) {
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/* Enable engine in normal mode. */
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writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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/* Wait for initial sequence complete. */
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ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
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adc_engine_control_reg_val,
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adc_engine_control_reg_val &
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ASPEED_ADC_CTRL_INIT_RDY,
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ASPEED_ADC_INIT_POLLING_TIME,
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ASPEED_ADC_INIT_TIMEOUT);
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if (ret)
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goto poll_timeout_error;
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}
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/* Start all channels in normal mode. */
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ret = clk_prepare_enable(data->clk_scaler->clk);
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if (ret)
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goto clk_enable_error;
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adc_engine_control_reg_val = GENMASK(31, 16) |
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ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
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writel(adc_engine_control_reg_val,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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model_data = of_device_get_match_data(&pdev->dev);
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indio_dev->name = model_data->model_name;
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indio_dev->dev.parent = &pdev->dev;
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indio_dev->info = &aspeed_adc_iio_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = aspeed_adc_iio_channels;
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indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
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ret = iio_device_register(indio_dev);
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if (ret)
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goto iio_register_error;
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return 0;
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iio_register_error:
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writel(ASPEED_OPERATION_MODE_POWER_DOWN,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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clk_disable_unprepare(data->clk_scaler->clk);
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clk_enable_error:
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poll_timeout_error:
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reset_control_assert(data->rst);
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reset_error:
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clk_hw_unregister_divider(data->clk_scaler);
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scaler_error:
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clk_hw_unregister_divider(data->clk_prescaler);
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return ret;
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}
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static int aspeed_adc_remove(struct platform_device *pdev)
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{
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struct iio_dev *indio_dev = platform_get_drvdata(pdev);
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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writel(ASPEED_OPERATION_MODE_POWER_DOWN,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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clk_disable_unprepare(data->clk_scaler->clk);
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reset_control_assert(data->rst);
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clk_hw_unregister_divider(data->clk_scaler);
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clk_hw_unregister_divider(data->clk_prescaler);
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return 0;
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}
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static const struct aspeed_adc_model_data ast2400_model_data = {
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.model_name = "ast2400-adc",
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.vref_voltage = 2500, // mV
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.min_sampling_rate = 10000,
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.max_sampling_rate = 500000,
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};
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static const struct aspeed_adc_model_data ast2500_model_data = {
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.model_name = "ast2500-adc",
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.vref_voltage = 1800, // mV
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.min_sampling_rate = 1,
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.max_sampling_rate = 1000000,
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.wait_init_sequence = true,
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};
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static const struct of_device_id aspeed_adc_matches[] = {
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{ .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
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{ .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
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static struct platform_driver aspeed_adc_driver = {
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.probe = aspeed_adc_probe,
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.remove = aspeed_adc_remove,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = aspeed_adc_matches,
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}
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};
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module_platform_driver(aspeed_adc_driver);
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MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
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MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
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MODULE_LICENSE("GPL");
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