207 lines
5.3 KiB
C
207 lines
5.3 KiB
C
/* linux/arch/arm/mach-s5p64x0/pm.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P64X0 Power Management Support
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*
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* Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/regs-timer.h>
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#include <plat/wakeup-mask.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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static struct sleep_save s5p64x0_core_save[] = {
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SAVE_ITEM(S5P64X0_APLL_CON),
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SAVE_ITEM(S5P64X0_MPLL_CON),
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SAVE_ITEM(S5P64X0_EPLL_CON),
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SAVE_ITEM(S5P64X0_EPLL_CON_K),
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SAVE_ITEM(S5P64X0_CLK_SRC0),
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SAVE_ITEM(S5P64X0_CLK_SRC1),
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SAVE_ITEM(S5P64X0_CLK_DIV0),
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SAVE_ITEM(S5P64X0_CLK_DIV1),
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SAVE_ITEM(S5P64X0_CLK_DIV2),
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SAVE_ITEM(S5P64X0_CLK_DIV3),
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SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
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SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
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SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
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};
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static struct sleep_save s5p64x0_misc_save[] = {
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SAVE_ITEM(S5P64X0_AHB_CON0),
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SAVE_ITEM(S5P64X0_SPCON0),
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SAVE_ITEM(S5P64X0_SPCON1),
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SAVE_ITEM(S5P64X0_MEM0CONSLP0),
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SAVE_ITEM(S5P64X0_MEM0CONSLP1),
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SAVE_ITEM(S5P64X0_MEM0DRVCON),
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SAVE_ITEM(S5P64X0_MEM1DRVCON),
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SAVE_ITEM(S3C64XX_TINT_CSTAT),
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};
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/* DPLL is present only in S5P6450 */
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static struct sleep_save s5p6450_core_save[] = {
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SAVE_ITEM(S5P6450_DPLL_CON),
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SAVE_ITEM(S5P6450_DPLL_CON_K),
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};
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void s3c_pm_configure_extint(void)
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{
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__raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
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}
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void s3c_pm_restore_core(void)
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{
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__raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
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s3c_pm_do_restore_core(s5p64x0_core_save,
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ARRAY_SIZE(s5p64x0_core_save));
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if (soc_is_s5p6450())
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s3c_pm_do_restore_core(s5p6450_core_save,
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ARRAY_SIZE(s5p6450_core_save));
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s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
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}
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void s3c_pm_save_core(void)
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{
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s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
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if (soc_is_s5p6450())
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s3c_pm_do_save(s5p6450_core_save,
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ARRAY_SIZE(s5p6450_core_save));
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s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
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}
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static int s5p64x0_cpu_suspend(unsigned long arg)
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{
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unsigned long tmp = 0;
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/*
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* Issue the standby signal into the pm unit. Note, we
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* issue a write-buffer drain just in case.
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*/
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asm("b 1f\n\t"
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".align 5\n\t"
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"1:\n\t"
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"mcr p15, 0, %0, c7, c10, 5\n\t"
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"mcr p15, 0, %0, c7, c10, 4\n\t"
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"mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
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/* we should never get past here */
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panic("sleep resumed to originator?");
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}
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/* mapping of interrupts to parts of the wakeup mask */
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static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
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{ .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, },
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{ .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, },
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{ .irq = IRQ_HSMMC0, .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, },
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{ .irq = IRQ_HSMMC1, .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, },
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};
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static void s5p64x0_pm_prepare(void)
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{
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u32 tmp;
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samsung_sync_wakemask(S5P64X0_PWR_CFG,
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s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
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/* store the resume address in INFORM0 register */
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__raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
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/* setup clock gating for FIMGVG block */
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__raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
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(S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
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__raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
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(S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
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/* Configure the stabilization counter with wait time required */
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__raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE);
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/* set WFI to SLEEP mode configuration */
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tmp = __raw_readl(S5P64X0_SLEEP_CFG);
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tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
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__raw_writel(tmp, S5P64X0_SLEEP_CFG);
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tmp = __raw_readl(S5P64X0_PWR_CFG);
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tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK);
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tmp |= S5P64X0_PWR_CFG_WFI_SLEEP;
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__raw_writel(tmp, S5P64X0_PWR_CFG);
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/*
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* set OTHERS register to disable interrupt before going to
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* sleep. This bit is present only in S5P6450, it is reserved
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* in S5P6440.
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*/
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if (soc_is_s5p6450()) {
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tmp = __raw_readl(S5P64X0_OTHERS);
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tmp |= S5P6450_OTHERS_DISABLE_INT;
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__raw_writel(tmp, S5P64X0_OTHERS);
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}
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/* ensure previous wakeup state is cleared before sleeping */
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__raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
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}
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static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
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{
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pm_cpu_prep = s5p64x0_pm_prepare;
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pm_cpu_sleep = s5p64x0_cpu_suspend;
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pm_uart_udivslot = 1;
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return 0;
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}
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static struct subsys_interface s5p64x0_pm_interface = {
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.name = "s5p64x0_pm",
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.subsys = &s5p64x0_subsys,
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.add_dev = s5p64x0_pm_add,
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};
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static __init int s5p64x0_pm_drvinit(void)
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{
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s3c_pm_init();
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return subsys_interface_register(&s5p64x0_pm_interface);
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}
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arch_initcall(s5p64x0_pm_drvinit);
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static void s5p64x0_pm_resume(void)
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{
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u32 tmp;
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tmp = __raw_readl(S5P64X0_OTHERS);
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tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
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S5P64X0_OTHERS_RET_UART);
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__raw_writel(tmp , S5P64X0_OTHERS);
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}
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static struct syscore_ops s5p64x0_pm_syscore_ops = {
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.resume = s5p64x0_pm_resume,
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};
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static __init int s5p64x0_pm_syscore_init(void)
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{
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register_syscore_ops(&s5p64x0_pm_syscore_ops);
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return 0;
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}
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arch_initcall(s5p64x0_pm_syscore_init);
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