221 lines
5.3 KiB
C
221 lines
5.3 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_KVM_VGIC_H
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#define __ASM_ARM_KVM_VGIC_H
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#include <linux/kernel.h>
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#include <linux/kvm.h>
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#include <linux/irqreturn.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/irqchip/arm-gic.h>
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#define VGIC_NR_IRQS 256
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#define VGIC_NR_SGIS 16
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#define VGIC_NR_PPIS 16
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#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
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#define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
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#define VGIC_MAX_CPUS KVM_MAX_VCPUS
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#define VGIC_MAX_LRS (1 << 6)
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/* Sanity checks... */
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#if (VGIC_MAX_CPUS > 8)
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#error Invalid number of CPU interfaces
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#endif
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#if (VGIC_NR_IRQS & 31)
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#error "VGIC_NR_IRQS must be a multiple of 32"
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#endif
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#if (VGIC_NR_IRQS > 1024)
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#error "VGIC_NR_IRQS must be <= 1024"
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#endif
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/*
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* The GIC distributor registers describing interrupts have two parts:
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* - 32 per-CPU interrupts (SGI + PPI)
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* - a bunch of shared interrupts (SPI)
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*/
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struct vgic_bitmap {
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union {
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u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
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DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
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} percpu[VGIC_MAX_CPUS];
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union {
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u32 reg[VGIC_NR_SHARED_IRQS / 32];
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DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
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} shared;
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};
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struct vgic_bytemap {
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u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
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u32 shared[VGIC_NR_SHARED_IRQS / 4];
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};
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struct vgic_dist {
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#ifdef CONFIG_KVM_ARM_VGIC
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spinlock_t lock;
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bool ready;
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/* Virtual control interface mapping */
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void __iomem *vctrl_base;
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/* Distributor and vcpu interface mapping in the guest */
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phys_addr_t vgic_dist_base;
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phys_addr_t vgic_cpu_base;
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/* Distributor enabled */
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u32 enabled;
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/* Interrupt enabled (one bit per IRQ) */
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struct vgic_bitmap irq_enabled;
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/* Interrupt 'pin' level */
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struct vgic_bitmap irq_state;
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/* Level-triggered interrupt in progress */
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struct vgic_bitmap irq_active;
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/* Interrupt priority. Not used yet. */
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struct vgic_bytemap irq_priority;
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/* Level/edge triggered */
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struct vgic_bitmap irq_cfg;
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/* Source CPU per SGI and target CPU */
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u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
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/* Target CPU for each IRQ */
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u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
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struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
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/* Bitmap indicating which CPU has something pending */
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unsigned long irq_pending_on_cpu;
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#endif
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};
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struct vgic_cpu {
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#ifdef CONFIG_KVM_ARM_VGIC
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/* per IRQ to LR mapping */
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u8 vgic_irq_lr_map[VGIC_NR_IRQS];
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/* Pending interrupts on this VCPU */
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DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
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DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
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/* Bitmap of used/free list registers */
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DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
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/* Number of list registers on this CPU */
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int nr_lr;
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/* CPU vif control registers for world switch */
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u32 vgic_hcr;
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u32 vgic_vmcr;
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u32 vgic_misr; /* Saved only */
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u32 vgic_eisr[2]; /* Saved only */
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u32 vgic_elrsr[2]; /* Saved only */
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u32 vgic_apr;
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u32 vgic_lr[VGIC_MAX_LRS];
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#endif
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};
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#define LR_EMPTY 0xff
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struct kvm;
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struct kvm_vcpu;
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struct kvm_run;
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struct kvm_exit_mmio;
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#ifdef CONFIG_KVM_ARM_VGIC
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int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
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int kvm_vgic_hyp_init(void);
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int kvm_vgic_init(struct kvm *kvm);
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int kvm_vgic_create(struct kvm *kvm);
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int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
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void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
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void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
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int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
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bool level);
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int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
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bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
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struct kvm_exit_mmio *mmio);
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#define irqchip_in_kernel(k) (!!((k)->arch.vgic.vctrl_base))
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#define vgic_initialized(k) ((k)->arch.vgic.ready)
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#else
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static inline int kvm_vgic_hyp_init(void)
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{
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return 0;
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}
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static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
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{
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return 0;
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}
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static inline int kvm_vgic_init(struct kvm *kvm)
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{
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return 0;
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}
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static inline int kvm_vgic_create(struct kvm *kvm)
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{
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return 0;
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}
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static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
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static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
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static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
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unsigned int irq_num, bool level)
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{
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return 0;
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}
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static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
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struct kvm_exit_mmio *mmio)
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{
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return false;
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}
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static inline int irqchip_in_kernel(struct kvm *kvm)
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{
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return 0;
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}
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static inline bool vgic_initialized(struct kvm *kvm)
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{
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return true;
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}
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#endif
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#endif
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