1098 lines
31 KiB
C
1098 lines
31 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Novatek NT35510 panel driver
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* Copyright (C) 2020 Linus Walleij <linus.walleij@linaro.org>
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* Based on code by Robert Teather (C) 2012 Samsung
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*
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* This display driver (and I refer to the physical component NT35510,
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* not this Linux kernel software driver) can handle:
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* 480x864, 480x854, 480x800, 480x720 and 480x640 pixel displays.
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* It has 480x840x24bit SRAM embedded for storing a frame.
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* When powered on the display is by default in 480x800 mode.
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*
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* The actual panels using this component have different names, but
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* the code needed to set up and configure the panel will be similar,
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* so they should all use the NT35510 driver with appropriate configuration
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* per-panel, e.g. for physical size.
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*
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* This driver is for the DSI interface to panels using the NT35510.
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*
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* The NT35510 can also use an RGB (DPI) interface combined with an
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* I2C or SPI interface for setting up the NT35510. If this is needed
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* this panel driver should be refactored to also support that use
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* case.
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*/
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#include <linux/backlight.h>
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#include <linux/bitops.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <video/mipi_display.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#include <drm/drm_print.h>
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#define MCS_CMD_MAUCCTR 0xF0 /* Manufacturer command enable */
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#define MCS_CMD_READ_ID1 0xDA
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#define MCS_CMD_READ_ID2 0xDB
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#define MCS_CMD_READ_ID3 0xDC
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#define MCS_CMD_MTP_READ_SETTING 0xF8 /* Uncertain about name */
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#define MCS_CMD_MTP_READ_PARAM 0xFF /* Uncertain about name */
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/*
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* These manufacturer commands are available after we enable manufacturer
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* command set (MCS) for page 0.
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*/
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#define NT35510_P0_DOPCTR 0xB1
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#define NT35510_P0_SDHDTCTR 0xB6
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#define NT35510_P0_GSEQCTR 0xB7
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#define NT35510_P0_SDEQCTR 0xB8
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#define NT35510_P0_SDVPCTR 0xBA
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#define NT35510_P0_DPFRCTR1 0xBD
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#define NT35510_P0_DPFRCTR2 0xBE
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#define NT35510_P0_DPFRCTR3 0xBF
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#define NT35510_P0_DPMCTR12 0xCC
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#define NT35510_P0_DOPCTR_LEN 2
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#define NT35510_P0_GSEQCTR_LEN 2
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#define NT35510_P0_SDEQCTR_LEN 4
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#define NT35510_P0_SDVPCTR_LEN 1
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#define NT35510_P0_DPFRCTR1_LEN 5
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#define NT35510_P0_DPFRCTR2_LEN 5
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#define NT35510_P0_DPFRCTR3_LEN 5
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#define NT35510_P0_DPMCTR12_LEN 3
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#define NT35510_DOPCTR_0_RAMKP BIT(7) /* Contents kept in sleep */
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#define NT35510_DOPCTR_0_DSITE BIT(6) /* Enable TE signal */
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#define NT35510_DOPCTR_0_DSIG BIT(5) /* Enable generic read/write */
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#define NT35510_DOPCTR_0_DSIM BIT(4) /* Enable video mode on DSI */
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#define NT35510_DOPCTR_0_EOTP BIT(3) /* Support EoTP */
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#define NT35510_DOPCTR_0_N565 BIT(2) /* RGB or BGR pixel format */
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#define NT35510_DOPCTR_1_TW_PWR_SEL BIT(4) /* TE power selector */
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#define NT35510_DOPCTR_1_CRGB BIT(3) /* RGB or BGR byte order */
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#define NT35510_DOPCTR_1_CTB BIT(2) /* Vertical scanning direction */
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#define NT35510_DOPCTR_1_CRL BIT(1) /* Source driver data shift */
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#define NT35510_P0_SDVPCTR_PRG BIT(2) /* 0 = normal operation, 1 = VGLO */
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#define NT35510_P0_SDVPCTR_AVDD 0 /* source driver output = AVDD */
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#define NT35510_P0_SDVPCTR_OFFCOL 1 /* source driver output = off color */
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#define NT35510_P0_SDVPCTR_AVSS 2 /* source driver output = AVSS */
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#define NT35510_P0_SDVPCTR_HI_Z 3 /* source driver output = High impedance */
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/*
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* These manufacturer commands are available after we enable manufacturer
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* command set (MCS) for page 1.
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*/
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#define NT35510_P1_SETAVDD 0xB0
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#define NT35510_P1_SETAVEE 0xB1
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#define NT35510_P1_SETVCL 0xB2
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#define NT35510_P1_SETVGH 0xB3
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#define NT35510_P1_SETVRGH 0xB4
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#define NT35510_P1_SETVGL 0xB5
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#define NT35510_P1_BT1CTR 0xB6
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#define NT35510_P1_BT2CTR 0xB7
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#define NT35510_P1_BT3CTR 0xB8
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#define NT35510_P1_BT4CTR 0xB9 /* VGH boosting times/freq */
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#define NT35510_P1_BT5CTR 0xBA
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#define NT35510_P1_PFMCTR 0xBB
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#define NT35510_P1_SETVGP 0xBC
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#define NT35510_P1_SETVGN 0xBD
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#define NT35510_P1_SETVCMOFF 0xBE
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#define NT35510_P1_VGHCTR 0xBF /* VGH output ctrl */
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#define NT35510_P1_SET_GAMMA_RED_POS 0xD1
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#define NT35510_P1_SET_GAMMA_GREEN_POS 0xD2
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#define NT35510_P1_SET_GAMMA_BLUE_POS 0xD3
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#define NT35510_P1_SET_GAMMA_RED_NEG 0xD4
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#define NT35510_P1_SET_GAMMA_GREEN_NEG 0xD5
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#define NT35510_P1_SET_GAMMA_BLUE_NEG 0xD6
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/* AVDD and AVEE setting 3 bytes */
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#define NT35510_P1_AVDD_LEN 3
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#define NT35510_P1_AVEE_LEN 3
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#define NT35510_P1_VGH_LEN 3
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#define NT35510_P1_VGL_LEN 3
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#define NT35510_P1_VGP_LEN 3
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#define NT35510_P1_VGN_LEN 3
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/* BT1CTR thru BT5CTR setting 3 bytes */
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#define NT35510_P1_BT1CTR_LEN 3
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#define NT35510_P1_BT2CTR_LEN 3
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#define NT35510_P1_BT4CTR_LEN 3
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#define NT35510_P1_BT5CTR_LEN 3
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/* 52 gamma parameters times two per color: positive and negative */
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#define NT35510_P1_GAMMA_LEN 52
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/**
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* struct nt35510_config - the display-specific NT35510 configuration
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*
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* Some of the settings provide an array of bytes, A, B C which mean:
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* A = normal / idle off mode
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* B = idle on mode
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* C = partial / idle off mode
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*
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* Gamma correction arrays are 10bit numbers, two consecutive bytes
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* makes out one point on the gamma correction curve. The points are
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* not linearly placed along the X axis, we get points 0, 1, 3, 5
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* 7, 11, 15, 23, 31, 47, 63, 95, 127, 128, 160, 192, 208, 224, 232,
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* 240, 244, 248, 250, 252, 254, 255. The voltages tuples form
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* V0, V1, V3 ... V255, with 0x0000 being the lowest voltage and
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* 0x03FF being the highest voltage.
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*
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* Each value must be strictly higher than the previous value forming
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* a rising curve like this:
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*
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* ^
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* | V255
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* | V254
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* | ....
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* | V5
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* | V3
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* | V1
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* | V0
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* +------------------------------------------->
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*
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* The details about all settings can be found in the NT35510 Application
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* Note.
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*/
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struct nt35510_config {
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/**
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* @width_mm: physical panel width [mm]
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*/
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u32 width_mm;
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/**
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* @height_mm: physical panel height [mm]
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*/
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u32 height_mm;
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/**
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* @mode: the display mode. This is only relevant outside the panel
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* in video mode: in command mode this is configuring the internal
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* timing in the display controller.
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*/
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const struct drm_display_mode mode;
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/**
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* @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V
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* in 0.1V steps the default is 0x05 which means 6.0V
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*/
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u8 avdd[NT35510_P1_AVDD_LEN];
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/**
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* @bt1ctr: setting for boost power control for the AVDD step-up
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* circuit (1)
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* bits 0..2 in the lower nibble controls PCK, the booster clock
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* frequency for the step-up circuit:
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* 0 = Hsync/32
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* 1 = Hsync/16
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* 2 = Hsync/8
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* 3 = Hsync/4
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* 4 = Hsync/2
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* 5 = Hsync
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* 6 = Hsync x 2
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* 7 = Hsync x 4
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* bits 4..6 in the upper nibble controls BTP, the boosting
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* amplification for the the step-up circuit:
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* 0 = Disable
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* 1 = 1.5 x VDDB
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* 2 = 1.66 x VDDB
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* 3 = 2 x VDDB
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* 4 = 2.5 x VDDB
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* 5 = 3 x VDDB
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* The defaults are 4 and 4 yielding 0x44
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*/
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u8 bt1ctr[NT35510_P1_BT1CTR_LEN];
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/**
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* @avee: setting for AVEE ranging from 0x00 = -6.5V to 0x14 = -4.5V
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* in 0.1V steps the default is 0x05 which means -6.0V
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*/
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u8 avee[NT35510_P1_AVEE_LEN];
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/**
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* @bt2ctr: setting for boost power control for the AVEE step-up
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* circuit (2)
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* bits 0..2 in the lower nibble controls NCK, the booster clock
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* frequency, the values are the same as for PCK in @bt1ctr.
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* bits 4..5 in the upper nibble controls BTN, the boosting
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* amplification for the the step-up circuit.
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* 0 = Disable
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* 1 = -1.5 x VDDB
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* 2 = -2 x VDDB
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* 3 = -2.5 x VDDB
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* 4 = -3 x VDDB
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* The defaults are 4 and 3 yielding 0x34
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*/
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u8 bt2ctr[NT35510_P1_BT2CTR_LEN];
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/**
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* @vgh: setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V
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* in 1V steps, the default is 0x08 which means 15V
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*/
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u8 vgh[NT35510_P1_VGH_LEN];
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/**
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* @bt4ctr: setting for boost power control for the VGH step-up
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* circuit (4)
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* bits 0..2 in the lower nibble controls HCK, the booster clock
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* frequency, the values are the same as for PCK in @bt1ctr.
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* bits 4..5 in the upper nibble controls BTH, the boosting
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* amplification for the the step-up circuit.
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* 0 = AVDD + VDDB
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* 1 = AVDD - AVEE
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* 2 = AVDD - AVEE + VDDB
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* 3 = AVDD x 2 - AVEE
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* The defaults are 4 and 3 yielding 0x34
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*/
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u8 bt4ctr[NT35510_P1_BT4CTR_LEN];
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/**
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* @vgl: setting for VGL ranging from 0x00 = -2V to 0x0f = -15V in
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* 1V steps, the default is 0x08 which means -10V
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*/
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u8 vgl[NT35510_P1_VGL_LEN];
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/**
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* @bt5ctr: setting for boost power control for the VGL step-up
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* circuit (5)
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* bits 0..2 in the lower nibble controls LCK, the booster clock
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* frequency, the values are the same as for PCK in @bt1ctr.
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* bits 4..5 in the upper nibble controls BTL, the boosting
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* amplification for the the step-up circuit.
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* 0 = AVEE + VCL
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* 1 = AVEE - AVDD
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* 2 = AVEE + VCL - AVDD
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* 3 = AVEE x 2 - AVDD
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* The defaults are 3 and 2 yielding 0x32
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*/
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u8 bt5ctr[NT35510_P1_BT5CTR_LEN];
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/**
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* @vgp: setting for VGP, the positive gamma divider voltages
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* VGMP the high voltage and VGSP the low voltage.
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* The first byte contains bit 8 of VGMP and VGSP in bits 4 and 0
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* The second byte contains bit 0..7 of VGMP
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* The third byte contains bit 0..7 of VGSP
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* VGMP 0x00 = 3.0V .. 0x108 = 6.3V in steps of 12.5mV
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* VGSP 0x00 = 0V .. 0x111 = 3.7V in steps of 12.5mV
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*/
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u8 vgp[NT35510_P1_VGP_LEN];
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/**
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* @vgn: setting for VGN, the negative gamma divider voltages,
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* same layout of bytes as @vgp.
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*/
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u8 vgn[NT35510_P1_VGN_LEN];
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/**
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* @sdeqctr: Source driver control settings, first byte is
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* 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and
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* mode 2 uses three steps meaning EQS3 is not used in mode
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* 1. Mode 2 is default. The last three parameters are EQS1, EQS2
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* and EQS3, setting the rise time for each equalizer step:
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* 0x00 = 0.0 us to 0x0f = 7.5 us in steps of 0.5us. The default
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* is 0x07 = 3.5 us.
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*/
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u8 sdeqctr[NT35510_P0_SDEQCTR_LEN];
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/**
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* @sdvpctr: power/voltage behaviour during vertical porch time
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*/
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u8 sdvpctr;
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/**
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* @t1: the number of pixel clocks on one scanline, range
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* 0x100 (258 ticks) .. 0x3FF (1024 ticks) so the value + 1
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* clock ticks.
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*/
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u16 t1;
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/**
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* @vbp: vertical back porch toward the PANEL note: not toward
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* the DSI host; these are separate interfaces, in from DSI host
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* and out to the panel.
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*/
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u8 vbp;
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/**
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* @vfp: vertical front porch toward the PANEL.
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*/
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u8 vfp;
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/**
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* @psel: pixel clock divisor: 0 = 1, 1 = 2, 2 = 4, 3 = 8.
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*/
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u8 psel;
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/**
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* @dpmctr12: Display timing control 12
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* Byte 1 bit 4 selects LVGL voltage level: 0 = VGLX, 1 = VGL_REG
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* Byte 1 bit 1 selects gate signal mode: 0 = non-overlap, 1 = overlap
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* Byte 1 bit 0 selects output signal control R/L swap, 0 = normal
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* 1 = swap all O->E, L->R
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* Byte 2 is CLW delay clock for CK O/E and CKB O/E signals:
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* 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
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* Byte 3 is FTI_H0 delay time for STP O/E signals:
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* 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
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*/
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u8 dpmctr12[NT35510_P0_DPMCTR12_LEN];
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/**
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* @gamma_corr_pos_r: Red gamma correction parameters, positive
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*/
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u8 gamma_corr_pos_r[NT35510_P1_GAMMA_LEN];
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/**
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* @gamma_corr_pos_g: Green gamma correction parameters, positive
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*/
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u8 gamma_corr_pos_g[NT35510_P1_GAMMA_LEN];
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/**
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* @gamma_corr_pos_b: Blue gamma correction parameters, positive
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*/
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u8 gamma_corr_pos_b[NT35510_P1_GAMMA_LEN];
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/**
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* @gamma_corr_neg_r: Red gamma correction parameters, negative
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*/
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u8 gamma_corr_neg_r[NT35510_P1_GAMMA_LEN];
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/**
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* @gamma_corr_neg_g: Green gamma correction parameters, negative
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*/
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u8 gamma_corr_neg_g[NT35510_P1_GAMMA_LEN];
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/**
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* @gamma_corr_neg_b: Blue gamma correction parameters, negative
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*/
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u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN];
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};
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/**
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* struct nt35510 - state container for the NT35510 panel
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*/
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struct nt35510 {
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/**
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* @dev: the container device
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*/
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struct device *dev;
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/**
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* @conf: the specific panel configuration, as the NT35510
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* can be combined with many physical panels, they can have
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* different physical dimensions and gamma correction etc,
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* so this is stored in the config.
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*/
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const struct nt35510_config *conf;
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/**
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* @panel: the DRM panel object for the instance
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*/
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struct drm_panel panel;
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/**
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* @supplies: regulators supplying the panel
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*/
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struct regulator_bulk_data supplies[2];
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/**
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* @reset_gpio: the reset line
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*/
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struct gpio_desc *reset_gpio;
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};
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/* Manufacturer command has strictly this byte sequence */
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static const u8 nt35510_mauc_select_page_0[] = { 0x55, 0xAA, 0x52, 0x08, 0x00 };
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static const u8 nt35510_mauc_select_page_1[] = { 0x55, 0xAA, 0x52, 0x08, 0x01 };
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static const u8 nt35510_vgh_on[] = { 0x01 };
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static inline struct nt35510 *panel_to_nt35510(struct drm_panel *panel)
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{
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return container_of(panel, struct nt35510, panel);
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}
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#define NT35510_ROTATE_0_SETTING 0x02
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#define NT35510_ROTATE_180_SETTING 0x00
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static int nt35510_send_long(struct nt35510 *nt, struct mipi_dsi_device *dsi,
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u8 cmd, u8 cmdlen, const u8 *seq)
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{
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const u8 *seqp = seq;
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int cmdwritten = 0;
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int chunk = cmdlen;
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int ret;
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if (chunk > 15)
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chunk = 15;
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ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk);
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if (ret < 0) {
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DRM_DEV_ERROR(nt->dev,
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"error sending DCS command seq cmd %02x\n",
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cmd);
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return ret;
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}
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cmdwritten += chunk;
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seqp += chunk;
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while (cmdwritten < cmdlen) {
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chunk = cmdlen - cmdwritten;
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if (chunk > 15)
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chunk = 15;
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ret = mipi_dsi_generic_write(dsi, seqp, chunk);
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if (ret < 0) {
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DRM_DEV_ERROR(nt->dev,
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"error sending generic write seq %02x\n",
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cmd);
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return ret;
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}
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cmdwritten += chunk;
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seqp += chunk;
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}
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DRM_DEV_DEBUG(nt->dev, "sent command %02x %02x bytes\n",
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cmd, cmdlen);
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return 0;
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}
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static int nt35510_read_id(struct nt35510 *nt)
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{
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
|
|
u8 id1, id2, id3;
|
|
int ret;
|
|
|
|
ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID1, &id1, 1);
|
|
if (ret < 0) {
|
|
DRM_DEV_ERROR(nt->dev, "could not read MTP ID1\n");
|
|
return ret;
|
|
}
|
|
ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID2, &id2, 1);
|
|
if (ret < 0) {
|
|
DRM_DEV_ERROR(nt->dev, "could not read MTP ID2\n");
|
|
return ret;
|
|
}
|
|
ret = mipi_dsi_dcs_read(dsi, MCS_CMD_READ_ID3, &id3, 1);
|
|
if (ret < 0) {
|
|
DRM_DEV_ERROR(nt->dev, "could not read MTP ID3\n");
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Multi-Time Programmable (?) memory contains manufacturer
|
|
* ID (e.g. Hydis 0x55), driver ID (e.g. NT35510 0xc0) and
|
|
* version.
|
|
*/
|
|
DRM_DEV_INFO(nt->dev,
|
|
"MTP ID manufacturer: %02x version: %02x driver: %02x\n",
|
|
id1, id2, id3);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* nt35510_setup_power() - set up power config in page 1
|
|
* @nt: the display instance to set up
|
|
*/
|
|
static int nt35510_setup_power(struct nt35510 *nt)
|
|
{
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
|
|
int ret;
|
|
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SETAVDD,
|
|
NT35510_P1_AVDD_LEN,
|
|
nt->conf->avdd);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_BT1CTR,
|
|
NT35510_P1_BT1CTR_LEN,
|
|
nt->conf->bt1ctr);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SETAVEE,
|
|
NT35510_P1_AVEE_LEN,
|
|
nt->conf->avee);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_BT2CTR,
|
|
NT35510_P1_BT2CTR_LEN,
|
|
nt->conf->bt2ctr);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGH,
|
|
NT35510_P1_VGH_LEN,
|
|
nt->conf->vgh);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_BT4CTR,
|
|
NT35510_P1_BT4CTR_LEN,
|
|
nt->conf->bt4ctr);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_VGHCTR,
|
|
ARRAY_SIZE(nt35510_vgh_on),
|
|
nt35510_vgh_on);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGL,
|
|
NT35510_P1_VGL_LEN,
|
|
nt->conf->vgl);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_BT5CTR,
|
|
NT35510_P1_BT5CTR_LEN,
|
|
nt->conf->bt5ctr);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGP,
|
|
NT35510_P1_VGP_LEN,
|
|
nt->conf->vgp);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SETVGN,
|
|
NT35510_P1_VGN_LEN,
|
|
nt->conf->vgn);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Typically 10 ms */
|
|
usleep_range(10000, 20000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* nt35510_setup_display() - set up display config in page 0
|
|
* @nt: the display instance to set up
|
|
*/
|
|
static int nt35510_setup_display(struct nt35510 *nt)
|
|
{
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
|
|
const struct nt35510_config *conf = nt->conf;
|
|
u8 dopctr[NT35510_P0_DOPCTR_LEN];
|
|
u8 gseqctr[NT35510_P0_GSEQCTR_LEN];
|
|
u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN];
|
|
/* FIXME: set up any rotation (assume none for now) */
|
|
u8 addr_mode = NT35510_ROTATE_0_SETTING;
|
|
u8 val;
|
|
int ret;
|
|
|
|
/* Enable TE, EoTP and RGB pixel format */
|
|
dopctr[0] = NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP |
|
|
NT35510_DOPCTR_0_N565;
|
|
dopctr[1] = NT35510_DOPCTR_1_CTB;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P0_DOPCTR,
|
|
NT35510_P0_DOPCTR_LEN,
|
|
dopctr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &addr_mode,
|
|
sizeof(addr_mode));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/*
|
|
* Source data hold time, default 0x05 = 2.5us
|
|
* 0x00..0x3F = 0 .. 31.5us in steps of 0.5us
|
|
* 0x0A = 5us
|
|
*/
|
|
val = 0x0A;
|
|
ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &val,
|
|
sizeof(val));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* EQ control for gate signals, 0x00 = 0 us */
|
|
gseqctr[0] = 0x00;
|
|
gseqctr[1] = 0x00;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P0_GSEQCTR,
|
|
NT35510_P0_GSEQCTR_LEN,
|
|
gseqctr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P0_SDEQCTR,
|
|
NT35510_P0_SDEQCTR_LEN,
|
|
conf->sdeqctr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDVPCTR,
|
|
&conf->sdvpctr, 1);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/*
|
|
* Display timing control for active and idle off mode:
|
|
* the first byte contains
|
|
* the two high bits of T1A and second byte the low 8 bits, and
|
|
* the valid range is 0x100 (257) to 0x3ff (1023) representing
|
|
* 258..1024 (+1) pixel clock ticks for one scanline. At 20MHz pixel
|
|
* clock this covers the range of 12.90us .. 51.20us in steps of
|
|
* 0.05us, the default is 0x184 (388) representing 389 ticks.
|
|
* The third byte is VBPDA, vertical back porch display active
|
|
* and the fourth VFPDA, vertical front porch display active,
|
|
* both given in number of scanlines in the range 0x02..0xff
|
|
* for 2..255 scanlines. The fifth byte is 2 bits selecting
|
|
* PSEL for active and idle off mode, how much the 20MHz clock
|
|
* is divided by 0..3. This needs to be adjusted to get the right
|
|
* frame rate.
|
|
*/
|
|
dpfrctr[0] = (conf->t1 >> 8) & 0xFF;
|
|
dpfrctr[1] = conf->t1 & 0xFF;
|
|
/* Vertical back porch */
|
|
dpfrctr[2] = conf->vbp;
|
|
/* Vertical front porch */
|
|
dpfrctr[3] = conf->vfp;
|
|
dpfrctr[4] = conf->psel;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR1,
|
|
NT35510_P0_DPFRCTR1_LEN,
|
|
dpfrctr);
|
|
if (ret)
|
|
return ret;
|
|
/* For idle and partial idle off mode we decrease front porch by one */
|
|
dpfrctr[3]--;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR2,
|
|
NT35510_P0_DPFRCTR2_LEN,
|
|
dpfrctr);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P0_DPFRCTR3,
|
|
NT35510_P0_DPFRCTR3_LEN,
|
|
dpfrctr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Enable TE on vblank */
|
|
ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Turn on the pads? */
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P0_DPMCTR12,
|
|
NT35510_P0_DPMCTR12_LEN,
|
|
conf->dpmctr12);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nt35510_set_brightness(struct backlight_device *bl)
|
|
{
|
|
struct nt35510 *nt = bl_get_data(bl);
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
|
|
u8 brightness = bl->props.brightness;
|
|
int ret;
|
|
|
|
DRM_DEV_DEBUG(nt->dev, "set brightness %d\n", brightness);
|
|
ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
|
|
&brightness,
|
|
sizeof(brightness));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct backlight_ops nt35510_bl_ops = {
|
|
.update_status = nt35510_set_brightness,
|
|
};
|
|
|
|
/*
|
|
* This power-on sequence
|
|
*/
|
|
static int nt35510_power_on(struct nt35510 *nt)
|
|
{
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
|
|
int ret;
|
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(nt->supplies), nt->supplies);
|
|
if (ret < 0) {
|
|
dev_err(nt->dev, "unable to enable regulators\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Toggle RESET in accordance with datasheet page 370 */
|
|
if (nt->reset_gpio) {
|
|
gpiod_set_value(nt->reset_gpio, 1);
|
|
/* Active min 10 us according to datasheet, let's say 20 */
|
|
usleep_range(20, 1000);
|
|
gpiod_set_value(nt->reset_gpio, 0);
|
|
/*
|
|
* 5 ms during sleep mode, 120 ms during sleep out mode
|
|
* according to datasheet, let's use 120-140 ms.
|
|
*/
|
|
usleep_range(120000, 140000);
|
|
}
|
|
|
|
ret = nt35510_read_id(nt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Set up stuff in manufacturer control, page 1 */
|
|
ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR,
|
|
ARRAY_SIZE(nt35510_mauc_select_page_1),
|
|
nt35510_mauc_select_page_1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nt35510_setup_power(nt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_POS,
|
|
NT35510_P1_GAMMA_LEN,
|
|
nt->conf->gamma_corr_pos_r);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_POS,
|
|
NT35510_P1_GAMMA_LEN,
|
|
nt->conf->gamma_corr_pos_g);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_POS,
|
|
NT35510_P1_GAMMA_LEN,
|
|
nt->conf->gamma_corr_pos_b);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_RED_NEG,
|
|
NT35510_P1_GAMMA_LEN,
|
|
nt->conf->gamma_corr_neg_r);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_GREEN_NEG,
|
|
NT35510_P1_GAMMA_LEN,
|
|
nt->conf->gamma_corr_neg_g);
|
|
if (ret)
|
|
return ret;
|
|
ret = nt35510_send_long(nt, dsi, NT35510_P1_SET_GAMMA_BLUE_NEG,
|
|
NT35510_P1_GAMMA_LEN,
|
|
nt->conf->gamma_corr_neg_b);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Set up stuff in manufacturer control, page 0 */
|
|
ret = nt35510_send_long(nt, dsi, MCS_CMD_MAUCCTR,
|
|
ARRAY_SIZE(nt35510_mauc_select_page_0),
|
|
nt35510_mauc_select_page_0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nt35510_setup_display(nt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nt35510_power_off(struct nt35510 *nt)
|
|
{
|
|
int ret;
|
|
|
|
ret = regulator_bulk_disable(ARRAY_SIZE(nt->supplies), nt->supplies);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (nt->reset_gpio)
|
|
gpiod_set_value(nt->reset_gpio, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nt35510_unprepare(struct drm_panel *panel)
|
|
{
|
|
struct nt35510 *nt = panel_to_nt35510(panel);
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
|
|
int ret;
|
|
|
|
ret = mipi_dsi_dcs_set_display_off(dsi);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(nt->dev, "failed to turn display off (%d)\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
usleep_range(10000, 20000);
|
|
|
|
/* Enter sleep mode */
|
|
ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(nt->dev, "failed to enter sleep mode (%d)\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
/* Wait 4 frames, how much is that 5ms in the vendor driver */
|
|
usleep_range(5000, 10000);
|
|
|
|
ret = nt35510_power_off(nt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nt35510_prepare(struct drm_panel *panel)
|
|
{
|
|
struct nt35510 *nt = panel_to_nt35510(panel);
|
|
struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
|
|
int ret;
|
|
|
|
ret = nt35510_power_on(nt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Exit sleep mode */
|
|
ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(nt->dev, "failed to exit sleep mode (%d)\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
/* Up to 120 ms */
|
|
usleep_range(120000, 150000);
|
|
|
|
ret = mipi_dsi_dcs_set_display_on(dsi);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(nt->dev, "failed to turn display on (%d)\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
/* Some 10 ms */
|
|
usleep_range(10000, 20000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nt35510_get_modes(struct drm_panel *panel,
|
|
struct drm_connector *connector)
|
|
{
|
|
struct nt35510 *nt = panel_to_nt35510(panel);
|
|
struct drm_display_mode *mode;
|
|
struct drm_display_info *info;
|
|
|
|
info = &connector->display_info;
|
|
info->width_mm = nt->conf->width_mm;
|
|
info->height_mm = nt->conf->height_mm;
|
|
mode = drm_mode_duplicate(connector->dev, &nt->conf->mode);
|
|
if (!mode) {
|
|
DRM_ERROR("bad mode or failed to add mode\n");
|
|
return -EINVAL;
|
|
}
|
|
drm_mode_set_name(mode);
|
|
mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
|
|
|
|
mode->width_mm = nt->conf->width_mm;
|
|
mode->height_mm = nt->conf->height_mm;
|
|
drm_mode_probed_add(connector, mode);
|
|
|
|
return 1; /* Number of modes */
|
|
}
|
|
|
|
static const struct drm_panel_funcs nt35510_drm_funcs = {
|
|
.unprepare = nt35510_unprepare,
|
|
.prepare = nt35510_prepare,
|
|
.get_modes = nt35510_get_modes,
|
|
};
|
|
|
|
static int nt35510_probe(struct mipi_dsi_device *dsi)
|
|
{
|
|
struct device *dev = &dsi->dev;
|
|
struct nt35510 *nt;
|
|
int ret;
|
|
|
|
nt = devm_kzalloc(dev, sizeof(struct nt35510), GFP_KERNEL);
|
|
if (!nt)
|
|
return -ENOMEM;
|
|
mipi_dsi_set_drvdata(dsi, nt);
|
|
nt->dev = dev;
|
|
|
|
dsi->lanes = 2;
|
|
dsi->format = MIPI_DSI_FMT_RGB888;
|
|
/*
|
|
* Datasheet suggests max HS rate for NT35510 is 250 MHz
|
|
* (period time 4ns, see figure 7.6.4 page 365) and max LP rate is
|
|
* 20 MHz (period time 50ns, see figure 7.6.6. page 366).
|
|
* However these frequencies appear in source code for the Hydis
|
|
* HVA40WV1 panel and setting up the LP frequency makes the panel
|
|
* not work.
|
|
*
|
|
* TODO: if other panels prove to be closer to the datasheet,
|
|
* maybe make this a per-panel config in struct nt35510_config?
|
|
*/
|
|
dsi->hs_rate = 349440000;
|
|
dsi->lp_rate = 9600000;
|
|
dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS |
|
|
MIPI_DSI_MODE_EOT_PACKET;
|
|
|
|
/*
|
|
* Every new incarnation of this display must have a unique
|
|
* data entry for the system in this driver.
|
|
*/
|
|
nt->conf = of_device_get_match_data(dev);
|
|
if (!nt->conf) {
|
|
dev_err(dev, "missing device configuration\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
nt->supplies[0].supply = "vdd"; /* 2.3-4.8 V */
|
|
nt->supplies[1].supply = "vddi"; /* 1.65-3.3V */
|
|
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(nt->supplies),
|
|
nt->supplies);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = regulator_set_voltage(nt->supplies[0].consumer,
|
|
2300000, 4800000);
|
|
if (ret)
|
|
return ret;
|
|
ret = regulator_set_voltage(nt->supplies[1].consumer,
|
|
1650000, 3300000);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nt->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
|
|
if (IS_ERR(nt->reset_gpio)) {
|
|
dev_err(dev, "error getting RESET GPIO\n");
|
|
return PTR_ERR(nt->reset_gpio);
|
|
}
|
|
|
|
drm_panel_init(&nt->panel, dev, &nt35510_drm_funcs,
|
|
DRM_MODE_CONNECTOR_DSI);
|
|
|
|
/*
|
|
* First, try to locate an external backlight (such as on GPIO)
|
|
* if this fails, assume we will want to use the internal backlight
|
|
* control.
|
|
*/
|
|
ret = drm_panel_of_backlight(&nt->panel);
|
|
if (ret) {
|
|
dev_err(dev, "error getting external backlight %d\n", ret);
|
|
return ret;
|
|
}
|
|
if (!nt->panel.backlight) {
|
|
struct backlight_device *bl;
|
|
|
|
bl = devm_backlight_device_register(dev, "nt35510", dev, nt,
|
|
&nt35510_bl_ops, NULL);
|
|
if (IS_ERR(bl)) {
|
|
DRM_DEV_ERROR(dev, "failed to register backlight device\n");
|
|
return PTR_ERR(bl);
|
|
}
|
|
bl->props.max_brightness = 255;
|
|
bl->props.brightness = 255;
|
|
bl->props.power = FB_BLANK_POWERDOWN;
|
|
nt->panel.backlight = bl;
|
|
}
|
|
|
|
ret = drm_panel_add(&nt->panel);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = mipi_dsi_attach(dsi);
|
|
if (ret < 0)
|
|
drm_panel_remove(&nt->panel);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nt35510_remove(struct mipi_dsi_device *dsi)
|
|
{
|
|
struct nt35510 *nt = mipi_dsi_get_drvdata(dsi);
|
|
int ret;
|
|
|
|
mipi_dsi_detach(dsi);
|
|
/* Power off */
|
|
ret = nt35510_power_off(nt);
|
|
drm_panel_remove(&nt->panel);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* These gamma correction values are 10bit tuples, so only bits 0 and 1 is
|
|
* ever used in the first byte. They form a positive and negative gamma
|
|
* correction curve for each color, values must be strictly higher for each
|
|
* step on the curve. As can be seen these default curves goes from 0x0001
|
|
* to 0x03FE.
|
|
*/
|
|
#define NT35510_GAMMA_POS_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \
|
|
0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \
|
|
0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \
|
|
0x83, 0x02, 0x78, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \
|
|
0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \
|
|
0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE
|
|
|
|
#define NT35510_GAMMA_NEG_DEFAULT 0x00, 0x01, 0x00, 0x43, 0x00, \
|
|
0x6B, 0x00, 0x87, 0x00, 0xA3, 0x00, 0xCE, 0x00, 0xF1, 0x01, \
|
|
0x27, 0x01, 0x53, 0x01, 0x98, 0x01, 0xCE, 0x02, 0x22, 0x02, \
|
|
0x43, 0x02, 0x50, 0x02, 0x9E, 0x02, 0xDD, 0x03, 0x00, 0x03, \
|
|
0x2E, 0x03, 0x54, 0x03, 0x7F, 0x03, 0x95, 0x03, 0xB3, 0x03, \
|
|
0xC2, 0x03, 0xE1, 0x03, 0xF1, 0x03, 0xFE
|
|
|
|
/*
|
|
* The Hydis HVA40WV1 panel
|
|
*/
|
|
static const struct nt35510_config nt35510_hydis_hva40wv1 = {
|
|
.width_mm = 52,
|
|
.height_mm = 86,
|
|
/**
|
|
* As the Hydis panel is used in command mode, the porches etc
|
|
* are settings programmed internally into the NT35510 controller
|
|
* and generated toward the physical display. As the panel is not
|
|
* used in video mode, these are not really exposed to the DSI
|
|
* host.
|
|
*
|
|
* Display frame rate control:
|
|
* Frame rate = (20 MHz / 1) / (389 * (7 + 50 + 800)) ~= 60 Hz
|
|
*/
|
|
.mode = {
|
|
/* The internal pixel clock of the NT35510 is 20 MHz */
|
|
.clock = 20000,
|
|
.hdisplay = 480,
|
|
.hsync_start = 480 + 2, /* HFP = 2 */
|
|
.hsync_end = 480 + 2 + 0, /* HSync = 0 */
|
|
.htotal = 480 + 2 + 0 + 5, /* HFP = 5 */
|
|
.vdisplay = 800,
|
|
.vsync_start = 800 + 2, /* VFP = 2 */
|
|
.vsync_end = 800 + 2 + 0, /* VSync = 0 */
|
|
.vtotal = 800 + 2 + 0 + 5, /* VBP = 5 */
|
|
.flags = 0,
|
|
},
|
|
/* 0x09: AVDD = 5.6V */
|
|
.avdd = { 0x09, 0x09, 0x09 },
|
|
/* 0x34: PCK = Hsync/2, BTP = 2 x VDDB */
|
|
.bt1ctr = { 0x34, 0x34, 0x34 },
|
|
/* 0x09: AVEE = -5.6V */
|
|
.avee = { 0x09, 0x09, 0x09 },
|
|
/* 0x24: NCK = Hsync/2, BTN = -2 x VDDB */
|
|
.bt2ctr = { 0x24, 0x24, 0x24 },
|
|
/* 0x05 = 12V */
|
|
.vgh = { 0x05, 0x05, 0x05 },
|
|
/* 0x24: NCKA = Hsync/2, VGH = 2 x AVDD - AVEE */
|
|
.bt4ctr = { 0x24, 0x24, 0x24 },
|
|
/* 0x0B = -13V */
|
|
.vgl = { 0x0B, 0x0B, 0x0B },
|
|
/* 0x24: LCKA = Hsync, VGL = AVDD + VCL - AVDD */
|
|
.bt5ctr = { 0x24, 0x24, 0x24 },
|
|
/* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */
|
|
.vgp = { 0x00, 0xA3, 0x00 },
|
|
/* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */
|
|
.vgn = { 0x00, 0xA3, 0x00 },
|
|
/* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */
|
|
.sdeqctr = { 0x01, 0x05, 0x05, 0x05 },
|
|
/* SDVPCTR: Normal operation off color during v porch */
|
|
.sdvpctr = 0x01,
|
|
/* T1: number of pixel clocks on one scanline: 0x184 = 389 clocks */
|
|
.t1 = 0x0184,
|
|
/* VBP: vertical back porch toward the panel */
|
|
.vbp = 7,
|
|
/* VFP: vertical front porch toward the panel */
|
|
.vfp = 50,
|
|
/* PSEL: divide pixel clock 20MHz with 1 (no clock downscaling) */
|
|
.psel = 0,
|
|
/* DPTMCTR12: 0x03: LVGL = VGLX, overlap mode, swap R->L O->E */
|
|
.dpmctr12 = { 0x03, 0x00, 0x00, },
|
|
/* Default gamma correction values */
|
|
.gamma_corr_pos_r = { NT35510_GAMMA_POS_DEFAULT },
|
|
.gamma_corr_pos_g = { NT35510_GAMMA_POS_DEFAULT },
|
|
.gamma_corr_pos_b = { NT35510_GAMMA_POS_DEFAULT },
|
|
.gamma_corr_neg_r = { NT35510_GAMMA_NEG_DEFAULT },
|
|
.gamma_corr_neg_g = { NT35510_GAMMA_NEG_DEFAULT },
|
|
.gamma_corr_neg_b = { NT35510_GAMMA_NEG_DEFAULT },
|
|
};
|
|
|
|
static const struct of_device_id nt35510_of_match[] = {
|
|
{
|
|
.compatible = "hydis,hva40wv1",
|
|
.data = &nt35510_hydis_hva40wv1,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, nt35510_of_match);
|
|
|
|
static struct mipi_dsi_driver nt35510_driver = {
|
|
.probe = nt35510_probe,
|
|
.remove = nt35510_remove,
|
|
.driver = {
|
|
.name = "panel-novatek-nt35510",
|
|
.of_match_table = nt35510_of_match,
|
|
},
|
|
};
|
|
module_mipi_dsi_driver(nt35510_driver);
|
|
|
|
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
|
|
MODULE_DESCRIPTION("NT35510-based panel driver");
|
|
MODULE_LICENSE("GPL v2");
|