567 lines
15 KiB
C
567 lines
15 KiB
C
/*
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* Copyright (C) 2015 Free Electrons
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* Copyright (C) 2015 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#include <linux/component.h>
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#include <linux/ioport.h>
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#include <linux/of_address.h>
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#include <linux/of_graph.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "sun4i_crtc.h"
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#include "sun4i_dotclock.h"
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#include "sun4i_drv.h"
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#include "sun4i_rgb.h"
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#include "sun4i_tcon.h"
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void sun4i_tcon_disable(struct sun4i_tcon *tcon)
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{
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DRM_DEBUG_DRIVER("Disabling TCON\n");
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/* Disable the TCON */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_TCON_ENABLE, 0);
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}
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EXPORT_SYMBOL(sun4i_tcon_disable);
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void sun4i_tcon_enable(struct sun4i_tcon *tcon)
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{
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DRM_DEBUG_DRIVER("Enabling TCON\n");
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/* Enable the TCON */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_TCON_ENABLE,
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SUN4I_TCON_GCTL_TCON_ENABLE);
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}
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EXPORT_SYMBOL(sun4i_tcon_enable);
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void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
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{
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/* Disable the TCON's channel */
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if (channel == 0) {
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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SUN4I_TCON0_CTL_TCON_ENABLE, 0);
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clk_disable_unprepare(tcon->dclk);
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} else if (channel == 1) {
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regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
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SUN4I_TCON1_CTL_TCON_ENABLE, 0);
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clk_disable_unprepare(tcon->sclk1);
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}
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}
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EXPORT_SYMBOL(sun4i_tcon_channel_disable);
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void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
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{
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/* Enable the TCON's channel */
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if (channel == 0) {
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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SUN4I_TCON0_CTL_TCON_ENABLE,
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SUN4I_TCON0_CTL_TCON_ENABLE);
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clk_prepare_enable(tcon->dclk);
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} else if (channel == 1) {
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regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
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SUN4I_TCON1_CTL_TCON_ENABLE,
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SUN4I_TCON1_CTL_TCON_ENABLE);
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clk_prepare_enable(tcon->sclk1);
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}
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}
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EXPORT_SYMBOL(sun4i_tcon_channel_enable);
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void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
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{
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u32 mask, val = 0;
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DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
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mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
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SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
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if (enable)
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val = mask;
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regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
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}
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EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
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static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
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int channel)
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{
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int delay = mode->vtotal - mode->vdisplay;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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delay /= 2;
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if (channel == 1)
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delay -= 2;
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delay = min(delay, 30);
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DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
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return delay;
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}
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void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
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struct drm_display_mode *mode)
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{
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unsigned int bp, hsync, vsync;
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u8 clk_delay;
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u32 val = 0;
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/* Adjust clock delay */
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clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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SUN4I_TCON0_CTL_CLK_DELAY_MASK,
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SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
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/* Set the resolution */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
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SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
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/*
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* This is called a backporch in the register documentation,
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* but it really is the front porch + hsync
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*/
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bp = mode->crtc_htotal - mode->crtc_hsync_start;
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DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
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mode->crtc_htotal, bp);
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/* Set horizontal display timings */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
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SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
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SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
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/*
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* This is called a backporch in the register documentation,
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* but it really is the front porch + hsync
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*/
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bp = mode->crtc_vtotal - mode->crtc_vsync_start;
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DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
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mode->crtc_vtotal, bp);
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/* Set vertical display timings */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
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SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal) |
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SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
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/* Set Hsync and Vsync length */
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hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
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vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
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DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
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SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
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SUN4I_TCON0_BASIC3_H_SYNC(hsync));
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/* Setup the polarity of the various signals */
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if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
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val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
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if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
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val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
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regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
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SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
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val);
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/* Map output pins to channel 0 */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_IOMAP_MASK,
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SUN4I_TCON_GCTL_IOMAP_TCON0);
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/* Enable the output on the pins */
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regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
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}
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EXPORT_SYMBOL(sun4i_tcon0_mode_set);
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void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
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struct drm_display_mode *mode)
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{
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unsigned int bp, hsync, vsync;
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u8 clk_delay;
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u32 val;
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/* Adjust clock delay */
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clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
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regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
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SUN4I_TCON1_CTL_CLK_DELAY_MASK,
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SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
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/* Set interlaced mode */
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
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else
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val = 0;
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regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
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SUN4I_TCON1_CTL_INTERLACE_ENABLE,
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val);
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/* Set the input resolution */
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
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SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
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SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
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/* Set the upscaling resolution */
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
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SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
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SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
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/* Set the output resolution */
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
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SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
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SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
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/* Set horizontal display timings */
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bp = mode->crtc_htotal - mode->crtc_hsync_end;
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DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
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mode->htotal, bp);
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
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SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
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SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
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/* Set vertical display timings */
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bp = mode->crtc_vtotal - mode->crtc_vsync_end;
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DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
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mode->vtotal, bp);
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
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SUN4I_TCON1_BASIC4_V_TOTAL(mode->vtotal) |
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SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
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/* Set Hsync and Vsync length */
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hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
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vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
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DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
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SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
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SUN4I_TCON1_BASIC5_H_SYNC(hsync));
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/* Map output pins to channel 1 */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_IOMAP_MASK,
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SUN4I_TCON_GCTL_IOMAP_TCON1);
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/*
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* FIXME: Undocumented bits
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*/
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if (tcon->has_mux)
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regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
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}
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EXPORT_SYMBOL(sun4i_tcon1_mode_set);
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static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
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struct sun4i_crtc *scrtc)
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{
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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if (scrtc->event) {
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drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
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drm_crtc_vblank_put(&scrtc->crtc);
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scrtc->event = NULL;
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}
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static irqreturn_t sun4i_tcon_handler(int irq, void *private)
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{
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struct sun4i_tcon *tcon = private;
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struct drm_device *drm = tcon->drm;
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struct sun4i_drv *drv = drm->dev_private;
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struct sun4i_crtc *scrtc = drv->crtc;
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unsigned int status;
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regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
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if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
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SUN4I_TCON_GINT0_VBLANK_INT(1))))
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return IRQ_NONE;
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drm_crtc_handle_vblank(&scrtc->crtc);
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sun4i_tcon_finish_page_flip(drm, scrtc);
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/* Acknowledge the interrupt */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
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SUN4I_TCON_GINT0_VBLANK_INT(0) |
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SUN4I_TCON_GINT0_VBLANK_INT(1),
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0);
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return IRQ_HANDLED;
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}
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static int sun4i_tcon_init_clocks(struct device *dev,
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struct sun4i_tcon *tcon)
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{
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tcon->clk = devm_clk_get(dev, "ahb");
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if (IS_ERR(tcon->clk)) {
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dev_err(dev, "Couldn't get the TCON bus clock\n");
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return PTR_ERR(tcon->clk);
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}
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clk_prepare_enable(tcon->clk);
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tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
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if (IS_ERR(tcon->sclk0)) {
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dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
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return PTR_ERR(tcon->sclk0);
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}
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tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
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if (IS_ERR(tcon->sclk1)) {
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dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
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return PTR_ERR(tcon->sclk1);
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}
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return sun4i_dclk_create(dev, tcon);
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}
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static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
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{
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sun4i_dclk_free(tcon);
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clk_disable_unprepare(tcon->clk);
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}
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static int sun4i_tcon_init_irq(struct device *dev,
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struct sun4i_tcon *tcon)
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{
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struct platform_device *pdev = to_platform_device(dev);
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int irq, ret;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
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return irq;
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}
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ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
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dev_name(dev), tcon);
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if (ret) {
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dev_err(dev, "Couldn't request the IRQ\n");
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return ret;
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}
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return 0;
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}
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static struct regmap_config sun4i_tcon_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x800,
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};
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static int sun4i_tcon_init_regmap(struct device *dev,
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struct sun4i_tcon *tcon)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res;
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void __iomem *regs;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(regs)) {
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dev_err(dev, "Couldn't map the TCON registers\n");
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return PTR_ERR(regs);
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}
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tcon->regs = devm_regmap_init_mmio(dev, regs,
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&sun4i_tcon_regmap_config);
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if (IS_ERR(tcon->regs)) {
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dev_err(dev, "Couldn't create the TCON regmap\n");
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return PTR_ERR(tcon->regs);
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}
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/* Make sure the TCON is disabled and all IRQs are off */
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regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
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regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
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regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
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/* Disable IO lines and set them to tristate */
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regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
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regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
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return 0;
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}
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static struct drm_panel *sun4i_tcon_find_panel(struct device_node *node)
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{
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struct device_node *port, *remote, *child;
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struct device_node *end_node = NULL;
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/* Inputs are listed first, then outputs */
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port = of_graph_get_port_by_id(node, 1);
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/*
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* Our first output is the RGB interface where the panel will
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* be connected.
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*/
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for_each_child_of_node(port, child) {
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u32 reg;
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of_property_read_u32(child, "reg", ®);
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if (reg == 0)
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end_node = child;
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}
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if (!end_node) {
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DRM_DEBUG_DRIVER("Missing panel endpoint\n");
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return ERR_PTR(-ENODEV);
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}
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remote = of_graph_get_remote_port_parent(end_node);
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if (!remote) {
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DRM_DEBUG_DRIVER("Unable to parse remote node\n");
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return ERR_PTR(-EINVAL);
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}
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return of_drm_find_panel(remote) ?: ERR_PTR(-EPROBE_DEFER);
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}
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static int sun4i_tcon_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct drm_device *drm = data;
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struct sun4i_drv *drv = drm->dev_private;
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struct sun4i_tcon *tcon;
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int ret;
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tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
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if (!tcon)
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return -ENOMEM;
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dev_set_drvdata(dev, tcon);
|
|
drv->tcon = tcon;
|
|
tcon->drm = drm;
|
|
|
|
if (of_device_is_compatible(dev->of_node, "allwinner,sun5i-a13-tcon"))
|
|
tcon->has_mux = true;
|
|
|
|
tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
|
|
if (IS_ERR(tcon->lcd_rst)) {
|
|
dev_err(dev, "Couldn't get our reset line\n");
|
|
return PTR_ERR(tcon->lcd_rst);
|
|
}
|
|
|
|
/* Make sure our TCON is reset */
|
|
if (!reset_control_status(tcon->lcd_rst))
|
|
reset_control_assert(tcon->lcd_rst);
|
|
|
|
ret = reset_control_deassert(tcon->lcd_rst);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't deassert our reset line\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = sun4i_tcon_init_regmap(dev, tcon);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't init our TCON regmap\n");
|
|
goto err_assert_reset;
|
|
}
|
|
|
|
ret = sun4i_tcon_init_clocks(dev, tcon);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't init our TCON clocks\n");
|
|
goto err_assert_reset;
|
|
}
|
|
|
|
ret = sun4i_tcon_init_irq(dev, tcon);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't init our TCON interrupts\n");
|
|
goto err_free_clocks;
|
|
}
|
|
|
|
tcon->panel = sun4i_tcon_find_panel(dev->of_node);
|
|
if (IS_ERR(tcon->panel)) {
|
|
dev_info(dev, "No panel found... RGB output disabled\n");
|
|
return 0;
|
|
}
|
|
|
|
ret = sun4i_rgb_init(drm);
|
|
if (ret < 0)
|
|
goto err_free_clocks;
|
|
|
|
return 0;
|
|
|
|
err_free_clocks:
|
|
sun4i_tcon_free_clocks(tcon);
|
|
err_assert_reset:
|
|
reset_control_assert(tcon->lcd_rst);
|
|
return ret;
|
|
}
|
|
|
|
static void sun4i_tcon_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct sun4i_tcon *tcon = dev_get_drvdata(dev);
|
|
|
|
sun4i_tcon_free_clocks(tcon);
|
|
}
|
|
|
|
static struct component_ops sun4i_tcon_ops = {
|
|
.bind = sun4i_tcon_bind,
|
|
.unbind = sun4i_tcon_unbind,
|
|
};
|
|
|
|
static int sun4i_tcon_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct drm_panel *panel;
|
|
|
|
/*
|
|
* The panel is not ready.
|
|
* Defer the probe.
|
|
*/
|
|
panel = sun4i_tcon_find_panel(node);
|
|
|
|
/*
|
|
* If we don't have a panel endpoint, just go on
|
|
*/
|
|
if (PTR_ERR(panel) == -EPROBE_DEFER) {
|
|
DRM_DEBUG_DRIVER("Still waiting for our panel. Deferring...\n");
|
|
return -EPROBE_DEFER;
|
|
}
|
|
|
|
return component_add(&pdev->dev, &sun4i_tcon_ops);
|
|
}
|
|
|
|
static int sun4i_tcon_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &sun4i_tcon_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sun4i_tcon_of_table[] = {
|
|
{ .compatible = "allwinner,sun5i-a13-tcon" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
|
|
|
|
static struct platform_driver sun4i_tcon_platform_driver = {
|
|
.probe = sun4i_tcon_probe,
|
|
.remove = sun4i_tcon_remove,
|
|
.driver = {
|
|
.name = "sun4i-tcon",
|
|
.of_match_table = sun4i_tcon_of_table,
|
|
},
|
|
};
|
|
module_platform_driver(sun4i_tcon_platform_driver);
|
|
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|
|
MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
|
|
MODULE_LICENSE("GPL");
|