650 lines
18 KiB
C
650 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Userspace interface for /dev/acrn_hsm - ACRN Hypervisor Service Module
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*
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* This file can be used by applications that need to communicate with the HSM
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* via the ioctl interface.
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*
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* Copyright (C) 2021 Intel Corporation. All rights reserved.
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*/
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#ifndef _UAPI_ACRN_H
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#define _UAPI_ACRN_H
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#include <linux/types.h>
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#define ACRN_IO_REQUEST_MAX 16
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#define ACRN_IOREQ_STATE_PENDING 0
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#define ACRN_IOREQ_STATE_COMPLETE 1
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#define ACRN_IOREQ_STATE_PROCESSING 2
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#define ACRN_IOREQ_STATE_FREE 3
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#define ACRN_IOREQ_TYPE_PORTIO 0
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#define ACRN_IOREQ_TYPE_MMIO 1
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#define ACRN_IOREQ_TYPE_PCICFG 2
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#define ACRN_IOREQ_DIR_READ 0
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#define ACRN_IOREQ_DIR_WRITE 1
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/**
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* struct acrn_mmio_request - Info of a MMIO I/O request
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* @direction: Access direction of this request (ACRN_IOREQ_DIR_*)
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* @reserved: Reserved for alignment and should be 0
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* @address: Access address of this MMIO I/O request
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* @size: Access size of this MMIO I/O request
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* @value: Read/write value of this MMIO I/O request
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*/
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struct acrn_mmio_request {
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__u32 direction;
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__u32 reserved;
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__u64 address;
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__u64 size;
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__u64 value;
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};
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/**
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* struct acrn_pio_request - Info of a PIO I/O request
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* @direction: Access direction of this request (ACRN_IOREQ_DIR_*)
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* @reserved: Reserved for alignment and should be 0
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* @address: Access address of this PIO I/O request
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* @size: Access size of this PIO I/O request
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* @value: Read/write value of this PIO I/O request
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*/
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struct acrn_pio_request {
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__u32 direction;
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__u32 reserved;
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__u64 address;
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__u64 size;
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__u32 value;
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};
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/**
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* struct acrn_pci_request - Info of a PCI I/O request
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* @direction: Access direction of this request (ACRN_IOREQ_DIR_*)
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* @reserved: Reserved for alignment and should be 0
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* @size: Access size of this PCI I/O request
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* @value: Read/write value of this PIO I/O request
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* @bus: PCI bus value of this PCI I/O request
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* @dev: PCI device value of this PCI I/O request
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* @func: PCI function value of this PCI I/O request
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* @reg: PCI config space offset of this PCI I/O request
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*
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* Need keep same header layout with &struct acrn_pio_request.
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*/
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struct acrn_pci_request {
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__u32 direction;
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__u32 reserved[3];
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__u64 size;
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__u32 value;
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__u32 bus;
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__u32 dev;
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__u32 func;
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__u32 reg;
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};
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/**
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* struct acrn_io_request - 256-byte ACRN I/O request
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* @type: Type of this request (ACRN_IOREQ_TYPE_*).
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* @completion_polling: Polling flag. Hypervisor will poll completion of the
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* I/O request if this flag set.
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* @reserved0: Reserved fields.
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* @reqs: Union of different types of request. Byte offset: 64.
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* @reqs.pio_request: PIO request data of the I/O request.
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* @reqs.pci_request: PCI configuration space request data of the I/O request.
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* @reqs.mmio_request: MMIO request data of the I/O request.
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* @reqs.data: Raw data of the I/O request.
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* @reserved1: Reserved fields.
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* @kernel_handled: Flag indicates this request need be handled in kernel.
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* @processed: The status of this request (ACRN_IOREQ_STATE_*).
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*
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* The state transitions of ACRN I/O request:
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*
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* FREE -> PENDING -> PROCESSING -> COMPLETE -> FREE -> ...
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*
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* An I/O request in COMPLETE or FREE state is owned by the hypervisor. HSM and
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* ACRN userspace are in charge of processing the others.
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*
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* On basis of the states illustrated above, a typical lifecycle of ACRN IO
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* request would look like:
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*
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* Flow (assume the initial state is FREE)
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* |
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* | Service VM vCPU 0 Service VM vCPU x User vCPU y
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* |
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* | hypervisor:
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* | fills in type, addr, etc.
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* | pauses the User VM vCPU y
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* | sets the state to PENDING (a)
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* | fires an upcall to Service VM
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* |
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* | HSM:
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* | scans for PENDING requests
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* | sets the states to PROCESSING (b)
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* | assigns the requests to clients (c)
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* V
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* | client:
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* | scans for the assigned requests
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* | handles the requests (d)
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* | HSM:
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* | sets states to COMPLETE
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* | notifies the hypervisor
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* |
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* | hypervisor:
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* | resumes User VM vCPU y (e)
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* |
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* | hypervisor:
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* | post handling (f)
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* V sets states to FREE
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*
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* Note that the procedures (a) to (f) in the illustration above require to be
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* strictly processed in the order. One vCPU cannot trigger another request of
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* I/O emulation before completing the previous one.
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*
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* Atomic and barriers are required when HSM and hypervisor accessing the state
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* of &struct acrn_io_request.
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*
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*/
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struct acrn_io_request {
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__u32 type;
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__u32 completion_polling;
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__u32 reserved0[14];
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union {
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struct acrn_pio_request pio_request;
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struct acrn_pci_request pci_request;
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struct acrn_mmio_request mmio_request;
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__u64 data[8];
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} reqs;
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__u32 reserved1;
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__u32 kernel_handled;
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__u32 processed;
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} __attribute__((aligned(256)));
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struct acrn_io_request_buffer {
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union {
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struct acrn_io_request req_slot[ACRN_IO_REQUEST_MAX];
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__u8 reserved[4096];
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};
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};
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/**
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* struct acrn_ioreq_notify - The structure of ioreq completion notification
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* @vmid: User VM ID
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* @reserved: Reserved and should be 0
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* @vcpu: vCPU ID
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*/
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struct acrn_ioreq_notify {
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__u16 vmid;
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__u16 reserved;
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__u32 vcpu;
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};
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/**
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* struct acrn_vm_creation - Info to create a User VM
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* @vmid: User VM ID returned from the hypervisor
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* @reserved0: Reserved and must be 0
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* @vcpu_num: Number of vCPU in the VM. Return from hypervisor.
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* @reserved1: Reserved and must be 0
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* @uuid: Empty space never to be used again (used to be UUID of the VM)
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* @vm_flag: Flag of the VM creating. Pass to hypervisor directly.
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* @ioreq_buf: Service VM GPA of I/O request buffer. Pass to
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* hypervisor directly.
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* @cpu_affinity: CPU affinity of the VM. Pass to hypervisor directly.
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* It's a bitmap which indicates CPUs used by the VM.
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*/
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struct acrn_vm_creation {
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__u16 vmid;
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__u16 reserved0;
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__u16 vcpu_num;
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__u16 reserved1;
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__u8 uuid[16];
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__u64 vm_flag;
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__u64 ioreq_buf;
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__u64 cpu_affinity;
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};
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/**
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* struct acrn_gp_regs - General registers of a User VM
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* @rax: Value of register RAX
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* @rcx: Value of register RCX
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* @rdx: Value of register RDX
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* @rbx: Value of register RBX
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* @rsp: Value of register RSP
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* @rbp: Value of register RBP
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* @rsi: Value of register RSI
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* @rdi: Value of register RDI
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* @r8: Value of register R8
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* @r9: Value of register R9
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* @r10: Value of register R10
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* @r11: Value of register R11
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* @r12: Value of register R12
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* @r13: Value of register R13
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* @r14: Value of register R14
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* @r15: Value of register R15
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*/
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struct acrn_gp_regs {
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__le64 rax;
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__le64 rcx;
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__le64 rdx;
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__le64 rbx;
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__le64 rsp;
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__le64 rbp;
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__le64 rsi;
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__le64 rdi;
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__le64 r8;
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__le64 r9;
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__le64 r10;
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__le64 r11;
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__le64 r12;
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__le64 r13;
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__le64 r14;
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__le64 r15;
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};
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/**
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* struct acrn_descriptor_ptr - Segment descriptor table of a User VM.
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* @limit: Limit field.
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* @base: Base field.
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* @reserved: Reserved and must be 0.
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*/
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struct acrn_descriptor_ptr {
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__le16 limit;
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__le64 base;
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__le16 reserved[3];
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} __attribute__ ((__packed__));
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/**
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* struct acrn_regs - Registers structure of a User VM
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* @gprs: General registers
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* @gdt: Global Descriptor Table
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* @idt: Interrupt Descriptor Table
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* @rip: Value of register RIP
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* @cs_base: Base of code segment selector
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* @cr0: Value of register CR0
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* @cr4: Value of register CR4
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* @cr3: Value of register CR3
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* @ia32_efer: Value of IA32_EFER MSR
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* @rflags: Value of regsiter RFLAGS
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* @reserved_64: Reserved and must be 0
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* @cs_ar: Attribute field of code segment selector
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* @cs_limit: Limit field of code segment selector
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* @reserved_32: Reserved and must be 0
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* @cs_sel: Value of code segment selector
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* @ss_sel: Value of stack segment selector
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* @ds_sel: Value of data segment selector
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* @es_sel: Value of extra segment selector
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* @fs_sel: Value of FS selector
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* @gs_sel: Value of GS selector
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* @ldt_sel: Value of LDT descriptor selector
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* @tr_sel: Value of TSS descriptor selector
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*/
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struct acrn_regs {
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struct acrn_gp_regs gprs;
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struct acrn_descriptor_ptr gdt;
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struct acrn_descriptor_ptr idt;
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__le64 rip;
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__le64 cs_base;
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__le64 cr0;
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__le64 cr4;
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__le64 cr3;
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__le64 ia32_efer;
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__le64 rflags;
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__le64 reserved_64[4];
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__le32 cs_ar;
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__le32 cs_limit;
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__le32 reserved_32[3];
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__le16 cs_sel;
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__le16 ss_sel;
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__le16 ds_sel;
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__le16 es_sel;
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__le16 fs_sel;
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__le16 gs_sel;
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__le16 ldt_sel;
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__le16 tr_sel;
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};
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/**
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* struct acrn_vcpu_regs - Info of vCPU registers state
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* @vcpu_id: vCPU ID
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* @reserved: Reserved and must be 0
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* @vcpu_regs: vCPU registers state
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*
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* This structure will be passed to hypervisor directly.
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*/
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struct acrn_vcpu_regs {
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__u16 vcpu_id;
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__u16 reserved[3];
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struct acrn_regs vcpu_regs;
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};
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#define ACRN_MEM_ACCESS_RIGHT_MASK 0x00000007U
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#define ACRN_MEM_ACCESS_READ 0x00000001U
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#define ACRN_MEM_ACCESS_WRITE 0x00000002U
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#define ACRN_MEM_ACCESS_EXEC 0x00000004U
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#define ACRN_MEM_ACCESS_RWX (ACRN_MEM_ACCESS_READ | \
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ACRN_MEM_ACCESS_WRITE | \
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ACRN_MEM_ACCESS_EXEC)
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#define ACRN_MEM_TYPE_MASK 0x000007C0U
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#define ACRN_MEM_TYPE_WB 0x00000040U
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#define ACRN_MEM_TYPE_WT 0x00000080U
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#define ACRN_MEM_TYPE_UC 0x00000100U
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#define ACRN_MEM_TYPE_WC 0x00000200U
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#define ACRN_MEM_TYPE_WP 0x00000400U
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/* Memory mapping types */
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#define ACRN_MEMMAP_RAM 0
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#define ACRN_MEMMAP_MMIO 1
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/**
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* struct acrn_vm_memmap - A EPT memory mapping info for a User VM.
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* @type: Type of the memory mapping (ACRM_MEMMAP_*).
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* Pass to hypervisor directly.
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* @attr: Attribute of the memory mapping.
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* Pass to hypervisor directly.
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* @user_vm_pa: Physical address of User VM.
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* Pass to hypervisor directly.
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* @service_vm_pa: Physical address of Service VM.
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* Pass to hypervisor directly.
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* @vma_base: VMA address of Service VM. Pass to hypervisor directly.
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* @len: Length of the memory mapping.
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* Pass to hypervisor directly.
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*/
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struct acrn_vm_memmap {
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__u32 type;
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__u32 attr;
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__u64 user_vm_pa;
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union {
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__u64 service_vm_pa;
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__u64 vma_base;
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};
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__u64 len;
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};
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/* Type of interrupt of a passthrough device */
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#define ACRN_PTDEV_IRQ_INTX 0
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#define ACRN_PTDEV_IRQ_MSI 1
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#define ACRN_PTDEV_IRQ_MSIX 2
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/**
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* struct acrn_ptdev_irq - Interrupt data of a passthrough device.
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* @type: Type (ACRN_PTDEV_IRQ_*)
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* @virt_bdf: Virtual Bus/Device/Function
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* @phys_bdf: Physical Bus/Device/Function
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* @intx: Info of interrupt
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* @intx.virt_pin: Virtual IOAPIC pin
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* @intx.phys_pin: Physical IOAPIC pin
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* @intx.is_pic_pin: Is PIC pin or not
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*
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* This structure will be passed to hypervisor directly.
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*/
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struct acrn_ptdev_irq {
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__u32 type;
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__u16 virt_bdf;
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__u16 phys_bdf;
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struct {
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__u32 virt_pin;
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__u32 phys_pin;
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__u32 is_pic_pin;
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} intx;
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};
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/* Type of PCI device assignment */
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#define ACRN_PTDEV_QUIRK_ASSIGN (1U << 0)
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#define ACRN_MMIODEV_RES_NUM 3
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#define ACRN_PCI_NUM_BARS 6
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/**
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* struct acrn_pcidev - Info for assigning or de-assigning a PCI device
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* @type: Type of the assignment
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* @virt_bdf: Virtual Bus/Device/Function
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* @phys_bdf: Physical Bus/Device/Function
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* @intr_line: PCI interrupt line
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* @intr_pin: PCI interrupt pin
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* @bar: PCI BARs.
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*
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* This structure will be passed to hypervisor directly.
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*/
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struct acrn_pcidev {
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__u32 type;
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__u16 virt_bdf;
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__u16 phys_bdf;
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__u8 intr_line;
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__u8 intr_pin;
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__u32 bar[ACRN_PCI_NUM_BARS];
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};
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/**
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* struct acrn_mmiodev - Info for assigning or de-assigning a MMIO device
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* @name: Name of the MMIO device.
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* @res[].user_vm_pa: Physical address of User VM of the MMIO region
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* for the MMIO device.
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* @res[].service_vm_pa: Physical address of Service VM of the MMIO
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* region for the MMIO device.
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* @res[].size: Size of the MMIO region for the MMIO device.
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* @res[].mem_type: Memory type of the MMIO region for the MMIO
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* device.
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*
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* This structure will be passed to hypervisor directly.
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*/
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struct acrn_mmiodev {
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__u8 name[8];
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struct {
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__u64 user_vm_pa;
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__u64 service_vm_pa;
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__u64 size;
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__u64 mem_type;
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} res[ACRN_MMIODEV_RES_NUM];
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};
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/**
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* struct acrn_vdev - Info for creating or destroying a virtual device
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* @id: Union of identifier of the virtual device
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* @id.value: Raw data of the identifier
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* @id.fields.vendor: Vendor id of the virtual PCI device
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* @id.fields.device: Device id of the virtual PCI device
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* @id.fields.legacy_id: ID of the virtual device if not a PCI device
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* @slot: Virtual Bus/Device/Function of the virtual
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* device
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* @io_base: IO resource base address of the virtual device
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* @io_size: IO resource size of the virtual device
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* @args: Arguments for the virtual device creation
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*
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* The created virtual device can be a PCI device or a legacy device (e.g.
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* a virtual UART controller) and it is emulated by the hypervisor. This
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* structure will be passed to hypervisor directly.
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*/
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struct acrn_vdev {
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/*
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* the identifier of the device, the low 32 bits represent the vendor
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* id and device id of PCI device and the high 32 bits represent the
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* device number of the legacy device
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*/
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union {
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__u64 value;
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struct {
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__le16 vendor;
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__le16 device;
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__le32 legacy_id;
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} fields;
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} id;
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__u64 slot;
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__u32 io_addr[ACRN_PCI_NUM_BARS];
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__u32 io_size[ACRN_PCI_NUM_BARS];
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__u8 args[128];
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};
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/**
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* struct acrn_msi_entry - Info for injecting a MSI interrupt to a VM
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* @msi_addr: MSI addr[19:12] with dest vCPU ID
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* @msi_data: MSI data[7:0] with vector
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*/
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struct acrn_msi_entry {
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__u64 msi_addr;
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__u64 msi_data;
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};
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struct acrn_acpi_generic_address {
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__u8 space_id;
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__u8 bit_width;
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__u8 bit_offset;
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__u8 access_size;
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__u64 address;
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} __attribute__ ((__packed__));
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/**
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* struct acrn_cstate_data - A C state package defined in ACPI
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* @cx_reg: Register of the C state object
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* @type: Type of the C state object
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* @latency: The worst-case latency to enter and exit this C state
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* @power: The average power consumption when in this C state
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*/
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struct acrn_cstate_data {
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struct acrn_acpi_generic_address cx_reg;
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__u8 type;
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__u32 latency;
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__u64 power;
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};
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/**
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* struct acrn_pstate_data - A P state package defined in ACPI
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* @core_frequency: CPU frequency (in MHz).
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* @power: Power dissipation (in milliwatts).
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* @transition_latency: The worst-case latency in microseconds that CPU is
|
|
* unavailable during a transition from any P state to
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|
* this P state.
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* @bus_master_latency: The worst-case latency in microseconds that Bus Masters
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|
* are prevented from accessing memory during a transition
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* from any P state to this P state.
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* @control: The value to be written to Performance Control Register
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* @status: Transition status.
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|
*/
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struct acrn_pstate_data {
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__u64 core_frequency;
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__u64 power;
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__u64 transition_latency;
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__u64 bus_master_latency;
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__u64 control;
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__u64 status;
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|
};
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|
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#define PMCMD_TYPE_MASK 0x000000ff
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enum acrn_pm_cmd_type {
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ACRN_PMCMD_GET_PX_CNT,
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ACRN_PMCMD_GET_PX_DATA,
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ACRN_PMCMD_GET_CX_CNT,
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ACRN_PMCMD_GET_CX_DATA,
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|
};
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|
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#define ACRN_IOEVENTFD_FLAG_PIO 0x01
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#define ACRN_IOEVENTFD_FLAG_DATAMATCH 0x02
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#define ACRN_IOEVENTFD_FLAG_DEASSIGN 0x04
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/**
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|
* struct acrn_ioeventfd - Data to operate a &struct hsm_ioeventfd
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|
* @fd: The fd of eventfd associated with a hsm_ioeventfd
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|
* @flags: Logical-OR of ACRN_IOEVENTFD_FLAG_*
|
|
* @addr: The start address of IO range of ioeventfd
|
|
* @len: The length of IO range of ioeventfd
|
|
* @reserved: Reserved and should be 0
|
|
* @data: Data for data matching
|
|
*
|
|
* Without flag ACRN_IOEVENTFD_FLAG_DEASSIGN, ioctl ACRN_IOCTL_IOEVENTFD
|
|
* creates a &struct hsm_ioeventfd with properties originated from &struct
|
|
* acrn_ioeventfd. With flag ACRN_IOEVENTFD_FLAG_DEASSIGN, ioctl
|
|
* ACRN_IOCTL_IOEVENTFD destroys the &struct hsm_ioeventfd matching the fd.
|
|
*/
|
|
struct acrn_ioeventfd {
|
|
__u32 fd;
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|
__u32 flags;
|
|
__u64 addr;
|
|
__u32 len;
|
|
__u32 reserved;
|
|
__u64 data;
|
|
};
|
|
|
|
#define ACRN_IRQFD_FLAG_DEASSIGN 0x01
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|
/**
|
|
* struct acrn_irqfd - Data to operate a &struct hsm_irqfd
|
|
* @fd: The fd of eventfd associated with a hsm_irqfd
|
|
* @flags: Logical-OR of ACRN_IRQFD_FLAG_*
|
|
* @msi: Info of MSI associated with the irqfd
|
|
*/
|
|
struct acrn_irqfd {
|
|
__s32 fd;
|
|
__u32 flags;
|
|
struct acrn_msi_entry msi;
|
|
};
|
|
|
|
/* The ioctl type, documented in ioctl-number.rst */
|
|
#define ACRN_IOCTL_TYPE 0xA2
|
|
|
|
/*
|
|
* Common IOCTL IDs definition for ACRN userspace
|
|
*/
|
|
#define ACRN_IOCTL_CREATE_VM \
|
|
_IOWR(ACRN_IOCTL_TYPE, 0x10, struct acrn_vm_creation)
|
|
#define ACRN_IOCTL_DESTROY_VM \
|
|
_IO(ACRN_IOCTL_TYPE, 0x11)
|
|
#define ACRN_IOCTL_START_VM \
|
|
_IO(ACRN_IOCTL_TYPE, 0x12)
|
|
#define ACRN_IOCTL_PAUSE_VM \
|
|
_IO(ACRN_IOCTL_TYPE, 0x13)
|
|
#define ACRN_IOCTL_RESET_VM \
|
|
_IO(ACRN_IOCTL_TYPE, 0x15)
|
|
#define ACRN_IOCTL_SET_VCPU_REGS \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x16, struct acrn_vcpu_regs)
|
|
|
|
#define ACRN_IOCTL_INJECT_MSI \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x23, struct acrn_msi_entry)
|
|
#define ACRN_IOCTL_VM_INTR_MONITOR \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x24, unsigned long)
|
|
#define ACRN_IOCTL_SET_IRQLINE \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x25, __u64)
|
|
|
|
#define ACRN_IOCTL_NOTIFY_REQUEST_FINISH \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x31, struct acrn_ioreq_notify)
|
|
#define ACRN_IOCTL_CREATE_IOREQ_CLIENT \
|
|
_IO(ACRN_IOCTL_TYPE, 0x32)
|
|
#define ACRN_IOCTL_ATTACH_IOREQ_CLIENT \
|
|
_IO(ACRN_IOCTL_TYPE, 0x33)
|
|
#define ACRN_IOCTL_DESTROY_IOREQ_CLIENT \
|
|
_IO(ACRN_IOCTL_TYPE, 0x34)
|
|
#define ACRN_IOCTL_CLEAR_VM_IOREQ \
|
|
_IO(ACRN_IOCTL_TYPE, 0x35)
|
|
|
|
#define ACRN_IOCTL_SET_MEMSEG \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x41, struct acrn_vm_memmap)
|
|
#define ACRN_IOCTL_UNSET_MEMSEG \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x42, struct acrn_vm_memmap)
|
|
|
|
#define ACRN_IOCTL_SET_PTDEV_INTR \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x53, struct acrn_ptdev_irq)
|
|
#define ACRN_IOCTL_RESET_PTDEV_INTR \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x54, struct acrn_ptdev_irq)
|
|
#define ACRN_IOCTL_ASSIGN_PCIDEV \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x55, struct acrn_pcidev)
|
|
#define ACRN_IOCTL_DEASSIGN_PCIDEV \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x56, struct acrn_pcidev)
|
|
#define ACRN_IOCTL_ASSIGN_MMIODEV \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x57, struct acrn_mmiodev)
|
|
#define ACRN_IOCTL_DEASSIGN_MMIODEV \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x58, struct acrn_mmiodev)
|
|
#define ACRN_IOCTL_CREATE_VDEV \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x59, struct acrn_vdev)
|
|
#define ACRN_IOCTL_DESTROY_VDEV \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x5A, struct acrn_vdev)
|
|
|
|
#define ACRN_IOCTL_PM_GET_CPU_STATE \
|
|
_IOWR(ACRN_IOCTL_TYPE, 0x60, __u64)
|
|
|
|
#define ACRN_IOCTL_IOEVENTFD \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x70, struct acrn_ioeventfd)
|
|
#define ACRN_IOCTL_IRQFD \
|
|
_IOW(ACRN_IOCTL_TYPE, 0x71, struct acrn_irqfd)
|
|
|
|
#endif /* _UAPI_ACRN_H */
|