679 lines
16 KiB
C
679 lines
16 KiB
C
/*
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* Driver for Zarlink DVB-T ZL10353 demodulator
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*
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* Copyright (C) 2006, 2007 Christopher Pascoe <c.pascoe@itee.uq.edu.au>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <asm/div64.h>
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#include <media/dvb_frontend.h>
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#include "zl10353_priv.h"
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#include "zl10353.h"
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struct zl10353_state {
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struct i2c_adapter *i2c;
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struct dvb_frontend frontend;
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struct zl10353_config config;
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u32 bandwidth;
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u32 ucblocks;
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u32 frequency;
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};
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static int debug;
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#define dprintk(args...) \
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do { \
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if (debug) printk(KERN_DEBUG "zl10353: " args); \
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} while (0)
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static int debug_regs;
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static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
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{
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struct zl10353_state *state = fe->demodulator_priv;
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u8 buf[2] = { reg, val };
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struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
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.buf = buf, .len = 2 };
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int err = i2c_transfer(state->i2c, &msg, 1);
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if (err != 1) {
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printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
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return err;
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}
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return 0;
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}
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static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
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{
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int err, i;
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for (i = 0; i < ilen - 1; i++)
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if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
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return err;
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return 0;
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}
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static int zl10353_read_register(struct zl10353_state *state, u8 reg)
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{
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int ret;
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u8 b0[1] = { reg };
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u8 b1[1] = { 0 };
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struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
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.flags = 0,
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.buf = b0, .len = 1 },
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{ .addr = state->config.demod_address,
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.flags = I2C_M_RD,
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.buf = b1, .len = 1 } };
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2) {
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printk("%s: readreg error (reg=%d, ret==%i)\n",
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__func__, reg, ret);
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return ret;
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}
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return b1[0];
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}
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static void zl10353_dump_regs(struct dvb_frontend *fe)
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{
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struct zl10353_state *state = fe->demodulator_priv;
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int ret;
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u8 reg;
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/* Dump all registers. */
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for (reg = 0; ; reg++) {
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if (reg % 16 == 0) {
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if (reg)
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printk(KERN_CONT "\n");
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printk(KERN_DEBUG "%02x:", reg);
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}
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ret = zl10353_read_register(state, reg);
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if (ret >= 0)
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printk(KERN_CONT " %02x", (u8)ret);
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else
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printk(KERN_CONT " --");
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if (reg == 0xff)
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break;
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}
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printk(KERN_CONT "\n");
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}
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static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
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u32 bandwidth,
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u16 *nominal_rate)
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{
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struct zl10353_state *state = fe->demodulator_priv;
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u32 adc_clock = 450560; /* 45.056 MHz */
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u64 value;
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u8 bw = bandwidth / 1000000;
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if (state->config.adc_clock)
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adc_clock = state->config.adc_clock;
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value = (u64)10 * (1 << 23) / 7 * 125;
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value = (bw * value) + adc_clock / 2;
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*nominal_rate = div_u64(value, adc_clock);
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dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
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__func__, bw, adc_clock, *nominal_rate);
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}
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static void zl10353_calc_input_freq(struct dvb_frontend *fe,
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u16 *input_freq)
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{
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struct zl10353_state *state = fe->demodulator_priv;
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u32 adc_clock = 450560; /* 45.056 MHz */
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int if2 = 361667; /* 36.1667 MHz */
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int ife;
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u64 value;
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if (state->config.adc_clock)
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adc_clock = state->config.adc_clock;
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if (state->config.if2)
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if2 = state->config.if2;
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if (adc_clock >= if2 * 2)
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ife = if2;
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else {
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ife = adc_clock - (if2 % adc_clock);
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if (ife > adc_clock / 2)
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ife = adc_clock - ife;
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}
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value = div_u64((u64)65536 * ife + adc_clock / 2, adc_clock);
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*input_freq = -value;
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dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
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__func__, if2, ife, adc_clock, -(int)value, *input_freq);
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}
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static int zl10353_sleep(struct dvb_frontend *fe)
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{
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static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };
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zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
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return 0;
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}
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static int zl10353_set_parameters(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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struct zl10353_state *state = fe->demodulator_priv;
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u16 nominal_rate, input_freq;
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u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
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u16 tps = 0;
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state->frequency = c->frequency;
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zl10353_single_write(fe, RESET, 0x80);
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udelay(200);
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zl10353_single_write(fe, 0xEA, 0x01);
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udelay(200);
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zl10353_single_write(fe, 0xEA, 0x00);
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zl10353_single_write(fe, AGC_TARGET, 0x28);
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if (c->transmission_mode != TRANSMISSION_MODE_AUTO)
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acq_ctl |= (1 << 0);
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if (c->guard_interval != GUARD_INTERVAL_AUTO)
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acq_ctl |= (1 << 1);
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zl10353_single_write(fe, ACQ_CTL, acq_ctl);
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switch (c->bandwidth_hz) {
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case 6000000:
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/* These are extrapolated from the 7 and 8MHz values */
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zl10353_single_write(fe, MCLK_RATIO, 0x97);
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zl10353_single_write(fe, 0x64, 0x34);
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zl10353_single_write(fe, 0xcc, 0xdd);
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break;
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case 7000000:
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zl10353_single_write(fe, MCLK_RATIO, 0x86);
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zl10353_single_write(fe, 0x64, 0x35);
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zl10353_single_write(fe, 0xcc, 0x73);
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break;
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default:
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c->bandwidth_hz = 8000000;
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/* fall through */
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case 8000000:
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zl10353_single_write(fe, MCLK_RATIO, 0x75);
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zl10353_single_write(fe, 0x64, 0x36);
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zl10353_single_write(fe, 0xcc, 0x73);
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}
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zl10353_calc_nominal_rate(fe, c->bandwidth_hz, &nominal_rate);
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zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
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zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
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state->bandwidth = c->bandwidth_hz;
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zl10353_calc_input_freq(fe, &input_freq);
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zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
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zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));
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/* Hint at TPS settings */
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switch (c->code_rate_HP) {
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case FEC_2_3:
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tps |= (1 << 7);
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break;
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case FEC_3_4:
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tps |= (2 << 7);
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break;
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case FEC_5_6:
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tps |= (3 << 7);
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break;
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case FEC_7_8:
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tps |= (4 << 7);
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break;
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case FEC_1_2:
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case FEC_AUTO:
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break;
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default:
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return -EINVAL;
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}
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switch (c->code_rate_LP) {
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case FEC_2_3:
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tps |= (1 << 4);
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break;
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case FEC_3_4:
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tps |= (2 << 4);
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break;
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case FEC_5_6:
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tps |= (3 << 4);
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break;
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case FEC_7_8:
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tps |= (4 << 4);
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break;
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case FEC_1_2:
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case FEC_AUTO:
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break;
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case FEC_NONE:
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if (c->hierarchy == HIERARCHY_AUTO ||
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c->hierarchy == HIERARCHY_NONE)
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break;
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/* fall through */
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default:
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return -EINVAL;
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}
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switch (c->modulation) {
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case QPSK:
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break;
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case QAM_AUTO:
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case QAM_16:
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tps |= (1 << 13);
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break;
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case QAM_64:
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tps |= (2 << 13);
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break;
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default:
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return -EINVAL;
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}
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switch (c->transmission_mode) {
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case TRANSMISSION_MODE_2K:
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case TRANSMISSION_MODE_AUTO:
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break;
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case TRANSMISSION_MODE_8K:
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tps |= (1 << 0);
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break;
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default:
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return -EINVAL;
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}
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switch (c->guard_interval) {
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case GUARD_INTERVAL_1_32:
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case GUARD_INTERVAL_AUTO:
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break;
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case GUARD_INTERVAL_1_16:
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tps |= (1 << 2);
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break;
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case GUARD_INTERVAL_1_8:
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tps |= (2 << 2);
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break;
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case GUARD_INTERVAL_1_4:
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tps |= (3 << 2);
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break;
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default:
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return -EINVAL;
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}
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switch (c->hierarchy) {
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case HIERARCHY_AUTO:
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case HIERARCHY_NONE:
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break;
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case HIERARCHY_1:
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tps |= (1 << 10);
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break;
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case HIERARCHY_2:
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tps |= (2 << 10);
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break;
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case HIERARCHY_4:
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tps |= (3 << 10);
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break;
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default:
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return -EINVAL;
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}
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zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
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zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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/*
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* If there is no tuner attached to the secondary I2C bus, we call
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* set_params to program a potential tuner attached somewhere else.
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* Otherwise, we update the PLL registers via calc_regs.
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*/
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if (state->config.no_tuner) {
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if (fe->ops.tuner_ops.set_params) {
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fe->ops.tuner_ops.set_params(fe);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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}
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} else if (fe->ops.tuner_ops.calc_regs) {
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fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
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pllbuf[1] <<= 1;
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zl10353_write(fe, pllbuf, sizeof(pllbuf));
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}
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zl10353_single_write(fe, 0x5F, 0x13);
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/* If no attached tuner or invalid PLL registers, just start the FSM. */
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if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL)
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zl10353_single_write(fe, FSM_GO, 0x01);
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else
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zl10353_single_write(fe, TUNER_GO, 0x01);
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return 0;
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}
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static int zl10353_get_parameters(struct dvb_frontend *fe,
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struct dtv_frontend_properties *c)
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{
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struct zl10353_state *state = fe->demodulator_priv;
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int s6, s9;
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u16 tps;
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static const u8 tps_fec_to_api[8] = {
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FEC_1_2,
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FEC_2_3,
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FEC_3_4,
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FEC_5_6,
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FEC_7_8,
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FEC_AUTO,
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FEC_AUTO,
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FEC_AUTO
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};
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s6 = zl10353_read_register(state, STATUS_6);
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s9 = zl10353_read_register(state, STATUS_9);
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if (s6 < 0 || s9 < 0)
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return -EREMOTEIO;
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if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0)
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return -EINVAL; /* no FE or TPS lock */
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tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 |
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zl10353_read_register(state, TPS_RECEIVED_0);
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c->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
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c->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
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switch ((tps >> 13) & 3) {
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case 0:
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c->modulation = QPSK;
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break;
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case 1:
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c->modulation = QAM_16;
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break;
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case 2:
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c->modulation = QAM_64;
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break;
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default:
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c->modulation = QAM_AUTO;
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break;
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}
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c->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
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TRANSMISSION_MODE_2K;
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switch ((tps >> 2) & 3) {
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case 0:
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c->guard_interval = GUARD_INTERVAL_1_32;
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break;
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case 1:
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c->guard_interval = GUARD_INTERVAL_1_16;
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break;
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case 2:
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c->guard_interval = GUARD_INTERVAL_1_8;
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break;
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case 3:
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c->guard_interval = GUARD_INTERVAL_1_4;
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break;
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default:
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c->guard_interval = GUARD_INTERVAL_AUTO;
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break;
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}
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switch ((tps >> 10) & 7) {
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case 0:
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c->hierarchy = HIERARCHY_NONE;
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break;
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case 1:
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c->hierarchy = HIERARCHY_1;
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break;
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case 2:
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c->hierarchy = HIERARCHY_2;
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break;
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case 3:
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c->hierarchy = HIERARCHY_4;
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break;
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default:
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c->hierarchy = HIERARCHY_AUTO;
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break;
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}
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c->frequency = state->frequency;
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c->bandwidth_hz = state->bandwidth;
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c->inversion = INVERSION_AUTO;
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return 0;
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}
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static int zl10353_read_status(struct dvb_frontend *fe, enum fe_status *status)
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{
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struct zl10353_state *state = fe->demodulator_priv;
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int s6, s7, s8;
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if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
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return -EREMOTEIO;
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if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
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return -EREMOTEIO;
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if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
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return -EREMOTEIO;
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*status = 0;
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if (s6 & (1 << 2))
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*status |= FE_HAS_CARRIER;
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if (s6 & (1 << 1))
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*status |= FE_HAS_VITERBI;
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if (s6 & (1 << 5))
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*status |= FE_HAS_LOCK;
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if (s7 & (1 << 4))
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*status |= FE_HAS_SYNC;
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if (s8 & (1 << 6))
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*status |= FE_HAS_SIGNAL;
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if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
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(FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
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*status &= ~FE_HAS_LOCK;
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return 0;
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}
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static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber)
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{
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struct zl10353_state *state = fe->demodulator_priv;
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*ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 |
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zl10353_read_register(state, RS_ERR_CNT_1) << 8 |
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zl10353_read_register(state, RS_ERR_CNT_0);
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return 0;
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}
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static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
|
|
{
|
|
struct zl10353_state *state = fe->demodulator_priv;
|
|
|
|
u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 |
|
|
zl10353_read_register(state, AGC_GAIN_0) << 2 | 3;
|
|
|
|
*strength = ~signal;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr)
|
|
{
|
|
struct zl10353_state *state = fe->demodulator_priv;
|
|
u8 _snr;
|
|
|
|
if (debug_regs)
|
|
zl10353_dump_regs(fe);
|
|
|
|
_snr = zl10353_read_register(state, SNR);
|
|
*snr = 10 * _snr / 8;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
|
|
{
|
|
struct zl10353_state *state = fe->demodulator_priv;
|
|
u32 ubl = 0;
|
|
|
|
ubl = zl10353_read_register(state, RS_UBC_1) << 8 |
|
|
zl10353_read_register(state, RS_UBC_0);
|
|
|
|
state->ucblocks += ubl;
|
|
*ucblocks = state->ucblocks;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zl10353_get_tune_settings(struct dvb_frontend *fe,
|
|
struct dvb_frontend_tune_settings
|
|
*fe_tune_settings)
|
|
{
|
|
fe_tune_settings->min_delay_ms = 1000;
|
|
fe_tune_settings->step_size = 0;
|
|
fe_tune_settings->max_drift = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zl10353_init(struct dvb_frontend *fe)
|
|
{
|
|
struct zl10353_state *state = fe->demodulator_priv;
|
|
u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };
|
|
|
|
if (debug_regs)
|
|
zl10353_dump_regs(fe);
|
|
if (state->config.parallel_ts)
|
|
zl10353_reset_attach[2] &= ~0x20;
|
|
if (state->config.clock_ctl_1)
|
|
zl10353_reset_attach[3] = state->config.clock_ctl_1;
|
|
if (state->config.pll_0)
|
|
zl10353_reset_attach[4] = state->config.pll_0;
|
|
|
|
/* Do a "hard" reset if not already done */
|
|
if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] ||
|
|
zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
|
|
zl10353_write(fe, zl10353_reset_attach,
|
|
sizeof(zl10353_reset_attach));
|
|
if (debug_regs)
|
|
zl10353_dump_regs(fe);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
|
|
{
|
|
struct zl10353_state *state = fe->demodulator_priv;
|
|
u8 val = 0x0a;
|
|
|
|
if (state->config.disable_i2c_gate_ctrl) {
|
|
/* No tuner attached to the internal I2C bus */
|
|
/* If set enable I2C bridge, the main I2C bus stopped hardly */
|
|
return 0;
|
|
}
|
|
|
|
if (enable)
|
|
val |= 0x10;
|
|
|
|
return zl10353_single_write(fe, 0x62, val);
|
|
}
|
|
|
|
static void zl10353_release(struct dvb_frontend *fe)
|
|
{
|
|
struct zl10353_state *state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static const struct dvb_frontend_ops zl10353_ops;
|
|
|
|
struct dvb_frontend *zl10353_attach(const struct zl10353_config *config,
|
|
struct i2c_adapter *i2c)
|
|
{
|
|
struct zl10353_state *state = NULL;
|
|
int id;
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
|
|
if (state == NULL)
|
|
goto error;
|
|
|
|
/* setup the state */
|
|
state->i2c = i2c;
|
|
memcpy(&state->config, config, sizeof(struct zl10353_config));
|
|
|
|
/* check if the demod is there */
|
|
id = zl10353_read_register(state, CHIP_ID);
|
|
if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
|
|
goto error;
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
|
|
return &state->frontend;
|
|
error:
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
|
|
static const struct dvb_frontend_ops zl10353_ops = {
|
|
.delsys = { SYS_DVBT },
|
|
.info = {
|
|
.name = "Zarlink ZL10353 DVB-T",
|
|
.frequency_min_hz = 174 * MHz,
|
|
.frequency_max_hz = 862 * MHz,
|
|
.frequency_stepsize_hz = 166667,
|
|
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
|
|
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
|
|
FE_CAN_FEC_AUTO |
|
|
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
|
|
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
|
|
FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
|
|
FE_CAN_MUTE_TS
|
|
},
|
|
|
|
.release = zl10353_release,
|
|
|
|
.init = zl10353_init,
|
|
.sleep = zl10353_sleep,
|
|
.i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
|
|
.write = zl10353_write,
|
|
|
|
.set_frontend = zl10353_set_parameters,
|
|
.get_frontend = zl10353_get_parameters,
|
|
.get_tune_settings = zl10353_get_tune_settings,
|
|
|
|
.read_status = zl10353_read_status,
|
|
.read_ber = zl10353_read_ber,
|
|
.read_signal_strength = zl10353_read_signal_strength,
|
|
.read_snr = zl10353_read_snr,
|
|
.read_ucblocks = zl10353_read_ucblocks,
|
|
};
|
|
|
|
module_param(debug, int, 0644);
|
|
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
|
|
|
|
module_param(debug_regs, int, 0644);
|
|
MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");
|
|
|
|
MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
|
|
MODULE_AUTHOR("Chris Pascoe");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
EXPORT_SYMBOL(zl10353_attach);
|