726 lines
18 KiB
C
726 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/types.h>
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#include "../../pci.h"
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#include "pcie-designware.h"
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/*
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* These interfaces resemble the pci_find_*capability() interfaces, but these
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* are for configuring host controllers, which are bridges *to* PCI devices but
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* are not PCI devices themselves.
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*/
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static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
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u8 cap)
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{
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u8 cap_id, next_cap_ptr;
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u16 reg;
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if (!cap_ptr)
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return 0;
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reg = dw_pcie_readw_dbi(pci, cap_ptr);
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cap_id = (reg & 0x00ff);
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if (cap_id > PCI_CAP_ID_MAX)
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return 0;
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if (cap_id == cap)
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return cap_ptr;
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next_cap_ptr = (reg & 0xff00) >> 8;
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return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
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}
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u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
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{
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u8 next_cap_ptr;
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u16 reg;
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reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
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next_cap_ptr = (reg & 0x00ff);
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return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
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}
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EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
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static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
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u8 cap)
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{
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u32 header;
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int ttl;
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int pos = PCI_CFG_SPACE_SIZE;
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/* minimum 8 bytes per capability */
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ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
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if (start)
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pos = start;
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header = dw_pcie_readl_dbi(pci, pos);
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/*
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* If we have no capabilities, this is indicated by cap ID,
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* cap version and next pointer all being 0.
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*/
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if (header == 0)
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return 0;
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while (ttl-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap && pos != start)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < PCI_CFG_SPACE_SIZE)
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break;
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header = dw_pcie_readl_dbi(pci, pos);
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}
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return 0;
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}
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u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
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{
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return dw_pcie_find_next_ext_capability(pci, 0, cap);
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}
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EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
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int dw_pcie_read(void __iomem *addr, int size, u32 *val)
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{
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if (!IS_ALIGNED((uintptr_t)addr, size)) {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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if (size == 4) {
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*val = readl(addr);
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} else if (size == 2) {
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*val = readw(addr);
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} else if (size == 1) {
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*val = readb(addr);
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} else {
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*val = 0;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(dw_pcie_read);
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int dw_pcie_write(void __iomem *addr, int size, u32 val)
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{
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if (!IS_ALIGNED((uintptr_t)addr, size))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (size == 4)
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writel(val, addr);
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else if (size == 2)
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writew(val, addr);
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else if (size == 1)
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writeb(val, addr);
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(dw_pcie_write);
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u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
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{
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int ret;
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u32 val;
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if (pci->ops->read_dbi)
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return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
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ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
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if (ret)
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dev_err(pci->dev, "Read DBI address failed\n");
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return val;
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}
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EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
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void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
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{
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int ret;
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if (pci->ops->write_dbi) {
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pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
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return;
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}
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ret = dw_pcie_write(pci->dbi_base + reg, size, val);
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if (ret)
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dev_err(pci->dev, "Write DBI address failed\n");
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}
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EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
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void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
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{
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int ret;
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if (pci->ops->write_dbi2) {
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pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
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return;
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}
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ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
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if (ret)
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dev_err(pci->dev, "write DBI address failed\n");
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}
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static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
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{
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int ret;
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u32 val;
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if (pci->ops->read_dbi)
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return pci->ops->read_dbi(pci, pci->atu_base, reg, 4);
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ret = dw_pcie_read(pci->atu_base + reg, 4, &val);
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if (ret)
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dev_err(pci->dev, "Read ATU address failed\n");
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return val;
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}
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static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
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{
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int ret;
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if (pci->ops->write_dbi) {
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pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val);
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return;
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}
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ret = dw_pcie_write(pci->atu_base + reg, 4, val);
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if (ret)
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dev_err(pci->dev, "Write ATU address failed\n");
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}
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static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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return dw_pcie_readl_atu(pci, offset + reg);
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}
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static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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dw_pcie_writel_atu(pci, offset + reg, val);
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}
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static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
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int index, int type,
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u64 cpu_addr, u64 pci_addr,
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u64 size)
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{
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u32 retries, val;
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u64 limit_addr = cpu_addr + size - 1;
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
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upper_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT,
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lower_32_bits(limit_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
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upper_32_bits(limit_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(pci_addr));
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val = type | PCIE_ATU_FUNC_NUM(func_no);
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val = upper_32_bits(size - 1) ?
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val | PCIE_ATU_INCREASE_REGION_SIZE : val;
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_ob_unroll(pci, index,
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PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "Outbound iATU is not being enabled\n");
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}
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static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
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int index, int type, u64 cpu_addr,
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u64 pci_addr, u64 size)
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{
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u32 retries, val;
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if (pci->ops->cpu_addr_fixup)
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cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
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if (pci->iatu_unroll_enabled) {
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dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type,
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cpu_addr, pci_addr, size);
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return;
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}
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dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
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PCIE_ATU_REGION_OUTBOUND | index);
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dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
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upper_32_bits(cpu_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
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lower_32_bits(cpu_addr + size - 1));
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dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
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lower_32_bits(pci_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
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upper_32_bits(pci_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
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PCIE_ATU_FUNC_NUM(func_no));
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
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if (val & PCIE_ATU_ENABLE)
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return;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "Outbound iATU is not being enabled\n");
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}
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void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
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u64 cpu_addr, u64 pci_addr, u64 size)
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{
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__dw_pcie_prog_outbound_atu(pci, 0, index, type,
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cpu_addr, pci_addr, size);
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}
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void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
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int type, u64 cpu_addr, u64 pci_addr,
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u32 size)
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{
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__dw_pcie_prog_outbound_atu(pci, func_no, index, type,
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cpu_addr, pci_addr, size);
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}
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static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
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return dw_pcie_readl_atu(pci, offset + reg);
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}
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static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
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dw_pcie_writel_atu(pci, offset + reg, val);
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}
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static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
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int index, int bar, u64 cpu_addr,
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enum dw_pcie_as_type as_type)
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{
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int type;
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u32 retries, val;
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(cpu_addr));
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switch (as_type) {
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case DW_PCIE_AS_MEM:
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type = PCIE_ATU_TYPE_MEM;
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break;
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case DW_PCIE_AS_IO:
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type = PCIE_ATU_TYPE_IO;
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break;
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default:
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return -EINVAL;
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}
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type |
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PCIE_ATU_FUNC_NUM(func_no));
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dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_FUNC_NUM_MATCH_EN |
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PCIE_ATU_ENABLE |
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PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_ib_unroll(pci, index,
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PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return 0;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "Inbound iATU is not being enabled\n");
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return -EBUSY;
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}
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int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
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int bar, u64 cpu_addr,
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enum dw_pcie_as_type as_type)
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{
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int type;
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u32 retries, val;
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if (pci->iatu_unroll_enabled)
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return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar,
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cpu_addr, as_type);
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dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
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index);
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dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
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dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
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switch (as_type) {
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case DW_PCIE_AS_MEM:
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type = PCIE_ATU_TYPE_MEM;
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break;
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case DW_PCIE_AS_IO:
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type = PCIE_ATU_TYPE_IO;
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break;
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default:
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return -EINVAL;
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}
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
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PCIE_ATU_FUNC_NUM(func_no));
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
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PCIE_ATU_FUNC_NUM_MATCH_EN |
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PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
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if (val & PCIE_ATU_ENABLE)
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return 0;
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mdelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "Inbound iATU is not being enabled\n");
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return -EBUSY;
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}
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void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
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enum dw_pcie_region_type type)
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{
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int region;
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switch (type) {
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case DW_PCIE_REGION_INBOUND:
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region = PCIE_ATU_REGION_INBOUND;
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break;
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case DW_PCIE_REGION_OUTBOUND:
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region = PCIE_ATU_REGION_OUTBOUND;
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break;
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default:
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return;
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}
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dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
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dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
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}
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int dw_pcie_wait_for_link(struct dw_pcie *pci)
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{
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int retries;
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/* Check if the link is up or not */
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for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
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if (dw_pcie_link_up(pci)) {
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dev_info(pci->dev, "Link up\n");
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return 0;
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}
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usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
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}
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dev_info(pci->dev, "Phy link never came up\n");
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|
|
|
return -ETIMEDOUT;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
|
|
|
|
int dw_pcie_link_up(struct dw_pcie *pci)
|
|
{
|
|
u32 val;
|
|
|
|
if (pci->ops->link_up)
|
|
return pci->ops->link_up(pci);
|
|
|
|
val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
|
|
return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
|
|
(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
|
|
}
|
|
|
|
void dw_pcie_upconfig_setup(struct dw_pcie *pci)
|
|
{
|
|
u32 val;
|
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
|
|
val |= PORT_MLTI_UPCFG_SUPPORT;
|
|
dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
|
|
|
|
static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
|
|
{
|
|
u32 cap, ctrl2, link_speed;
|
|
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
|
|
|
cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
|
|
ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
|
|
ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
|
|
|
|
switch (pcie_link_speed[link_gen]) {
|
|
case PCIE_SPEED_2_5GT:
|
|
link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
|
|
break;
|
|
case PCIE_SPEED_5_0GT:
|
|
link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
|
|
break;
|
|
case PCIE_SPEED_8_0GT:
|
|
link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
|
|
break;
|
|
case PCIE_SPEED_16_0GT:
|
|
link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
|
|
break;
|
|
default:
|
|
/* Use hardware capability */
|
|
link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
|
|
ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
|
|
break;
|
|
}
|
|
|
|
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
|
|
|
|
cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
|
|
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
|
|
|
|
}
|
|
|
|
static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
|
|
{
|
|
u32 val;
|
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
|
|
if (val == 0xffffffff)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci)
|
|
{
|
|
int max_region, i, ob = 0, ib = 0;
|
|
u32 val;
|
|
|
|
max_region = min((int)pci->atu_size / 512, 256);
|
|
|
|
for (i = 0; i < max_region; i++) {
|
|
dw_pcie_writel_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET,
|
|
0x11110000);
|
|
|
|
val = dw_pcie_readl_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET);
|
|
if (val == 0x11110000)
|
|
ob++;
|
|
else
|
|
break;
|
|
}
|
|
|
|
for (i = 0; i < max_region; i++) {
|
|
dw_pcie_writel_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET,
|
|
0x11110000);
|
|
|
|
val = dw_pcie_readl_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET);
|
|
if (val == 0x11110000)
|
|
ib++;
|
|
else
|
|
break;
|
|
}
|
|
pci->num_ib_windows = ib;
|
|
pci->num_ob_windows = ob;
|
|
}
|
|
|
|
static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
|
|
{
|
|
int max_region, i, ob = 0, ib = 0;
|
|
u32 val;
|
|
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
|
|
max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
|
|
|
|
for (i = 0; i < max_region; i++) {
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | i);
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000);
|
|
val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET);
|
|
if (val == 0x11110000)
|
|
ob++;
|
|
else
|
|
break;
|
|
}
|
|
|
|
for (i = 0; i < max_region; i++) {
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | i);
|
|
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000);
|
|
val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET);
|
|
if (val == 0x11110000)
|
|
ib++;
|
|
else
|
|
break;
|
|
}
|
|
|
|
pci->num_ib_windows = ib;
|
|
pci->num_ob_windows = ob;
|
|
}
|
|
|
|
void dw_pcie_setup(struct dw_pcie *pci)
|
|
{
|
|
u32 val;
|
|
struct device *dev = pci->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
if (pci->version >= 0x480A || (!pci->version &&
|
|
dw_pcie_iatu_unroll_enabled(pci))) {
|
|
pci->iatu_unroll_enabled = true;
|
|
if (!pci->atu_base) {
|
|
struct resource *res =
|
|
platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
|
|
if (res)
|
|
pci->atu_size = resource_size(res);
|
|
pci->atu_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(pci->atu_base))
|
|
pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
|
|
}
|
|
|
|
if (!pci->atu_size)
|
|
/* Pick a minimal default, enough for 8 in and 8 out windows */
|
|
pci->atu_size = SZ_4K;
|
|
|
|
dw_pcie_iatu_detect_regions_unroll(pci);
|
|
} else
|
|
dw_pcie_iatu_detect_regions(pci);
|
|
|
|
dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
|
|
"enabled" : "disabled");
|
|
|
|
dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound",
|
|
pci->num_ob_windows, pci->num_ib_windows);
|
|
|
|
if (pci->link_gen > 0)
|
|
dw_pcie_link_set_max_speed(pci, pci->link_gen);
|
|
|
|
/* Configure Gen1 N_FTS */
|
|
if (pci->n_fts[0]) {
|
|
val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
|
|
val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
|
|
val |= PORT_AFR_N_FTS(pci->n_fts[0]);
|
|
val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
|
|
dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
|
|
}
|
|
|
|
/* Configure Gen2+ N_FTS */
|
|
if (pci->n_fts[1]) {
|
|
val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
|
|
val &= ~PORT_LOGIC_N_FTS_MASK;
|
|
val |= pci->n_fts[pci->link_gen - 1];
|
|
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
|
|
}
|
|
|
|
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
|
|
val &= ~PORT_LINK_FAST_LINK_MODE;
|
|
val |= PORT_LINK_DLL_LINK_EN;
|
|
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
|
|
|
|
of_property_read_u32(np, "num-lanes", &pci->num_lanes);
|
|
if (!pci->num_lanes) {
|
|
dev_dbg(pci->dev, "Using h/w default number of lanes\n");
|
|
return;
|
|
}
|
|
|
|
/* Set the number of lanes */
|
|
val &= ~PORT_LINK_FAST_LINK_MODE;
|
|
val &= ~PORT_LINK_MODE_MASK;
|
|
switch (pci->num_lanes) {
|
|
case 1:
|
|
val |= PORT_LINK_MODE_1_LANES;
|
|
break;
|
|
case 2:
|
|
val |= PORT_LINK_MODE_2_LANES;
|
|
break;
|
|
case 4:
|
|
val |= PORT_LINK_MODE_4_LANES;
|
|
break;
|
|
case 8:
|
|
val |= PORT_LINK_MODE_8_LANES;
|
|
break;
|
|
default:
|
|
dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
|
|
return;
|
|
}
|
|
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
|
|
|
|
/* Set link width speed control register */
|
|
val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
|
|
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
|
|
switch (pci->num_lanes) {
|
|
case 1:
|
|
val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
|
|
break;
|
|
case 2:
|
|
val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
|
|
break;
|
|
case 4:
|
|
val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
|
|
break;
|
|
case 8:
|
|
val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
|
|
break;
|
|
}
|
|
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
|
|
|
|
if (of_property_read_bool(np, "snps,enable-cdm-check")) {
|
|
val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
|
|
val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
|
|
PCIE_PL_CHK_REG_CHK_REG_START;
|
|
dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
|
|
}
|
|
}
|