458 lines
12 KiB
C
458 lines
12 KiB
C
/* pci-vdk.c: MB93090-MB00 (VDK) PCI support
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*
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* Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <asm/segment.h>
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#include <asm/io.h>
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#include <asm/mb-regs.h>
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#include <asm/mb86943a.h>
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#include "pci-frv.h"
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unsigned int __nongpreldata pci_probe = 1;
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int __nongpreldata pcibios_last_bus = -1;
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struct pci_bus *__nongpreldata pci_root_bus;
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struct pci_ops *__nongpreldata pci_root_ops;
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/*
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* The accessible PCI window does not cover the entire CPU address space, but
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* there are devices we want to access outside of that window, so we need to
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* insert specific PCI bus resources instead of using the platform-level bus
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* resources directly for the PCI root bus.
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*
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* These are configured and inserted by pcibios_init() and are attached to the
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* root bus by pcibios_fixup_bus().
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*/
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static struct resource pci_ioport_resource = {
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.name = "PCI IO",
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.start = 0,
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.end = IO_SPACE_LIMIT,
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.flags = IORESOURCE_IO,
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};
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static struct resource pci_iomem_resource = {
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.name = "PCI mem",
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.start = 0,
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.end = -1,
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.flags = IORESOURCE_MEM,
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};
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/*
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* Functions for accessing PCI configuration space
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*/
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#define CONFIG_CMD(bus, dev, where) \
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(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
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#define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)
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#define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
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#define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
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#define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)
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#define __set_PciCfgDataB(A,V) \
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writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
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#define __set_PciCfgDataW(A,V) \
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writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
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#define __set_PciCfgDataL(A,V) \
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writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
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#define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
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#define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
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#define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))
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#define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
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#define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
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#define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
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static inline int __query(const struct pci_dev *dev)
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{
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// return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
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// return dev->bus->number==1;
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// return dev->bus->number==0 &&
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// (dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0));
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return 0;
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}
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/*****************************************************************************/
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/*
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*
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*/
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static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
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u32 *val)
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{
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u32 _value;
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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_value = __get_PciBridgeDataL(where & ~3);
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}
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else {
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__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
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_value = __get_PciCfgDataL(where & ~3);
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}
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switch (size) {
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case 1:
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_value = _value >> ((where & 3) * 8);
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break;
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case 2:
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_value = _value >> ((where & 2) * 8);
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break;
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case 4:
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break;
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default:
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BUG();
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}
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*val = _value;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
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u32 value)
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{
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switch (size) {
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case 1:
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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__set_PciBridgeDataB(where, value);
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}
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else {
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__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
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__set_PciCfgDataB(where, value);
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}
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break;
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case 2:
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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__set_PciBridgeDataW(where, value);
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}
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else {
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__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
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__set_PciCfgDataW(where, value);
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}
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break;
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case 4:
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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__set_PciBridgeDataL(where, value);
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}
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else {
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__set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
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__set_PciCfgDataL(where, value);
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}
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break;
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default:
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BUG();
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_direct_frv = {
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pci_frv_read_config,
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pci_frv_write_config,
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};
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/*
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* Before we decide to use direct hardware access mechanisms, we try to do some
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* trivial checks to ensure it at least _seems_ to be working -- we just test
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* whether bus 00 contains a host bridge (this is similar to checking
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* techniques used in XFree86, but ours should be more reliable since we
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* attempt to make use of direct access hints provided by the PCI BIOS).
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*
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* This should be close to trivial, but it isn't, because there are buggy
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* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
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*/
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static int __init pci_sanity_check(struct pci_ops *o)
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{
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struct pci_bus bus; /* Fake bus and device */
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u32 id;
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bus.number = 0;
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if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) {
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printk("PCI: VDK Bridge device:vendor: %08x\n", id);
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if (id == 0x200e10cf)
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return 1;
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}
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printk("PCI: VDK Bridge: Sanity check failed\n");
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return 0;
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}
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static struct pci_ops * __init pci_check_direct(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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/* check if access works */
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if (pci_sanity_check(&pci_direct_frv)) {
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local_irq_restore(flags);
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printk("PCI: Using configuration frv\n");
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// request_mem_region(0xBE040000, 256, "FRV bridge");
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// request_mem_region(0xBFFFFFF4, 12, "PCI frv");
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return &pci_direct_frv;
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}
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local_irq_restore(flags);
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return NULL;
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}
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/*
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* Discover remaining PCI buses in case there are peer host bridges.
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* We use the number of last PCI bus provided by the PCI BIOS.
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*/
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static void __init pcibios_fixup_peer_bridges(void)
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{
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struct pci_bus bus;
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struct pci_dev dev;
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int n;
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u16 l;
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if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
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return;
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printk("PCI: Peer bridge fixup\n");
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for (n=0; n <= pcibios_last_bus; n++) {
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if (pci_find_bus(0, n))
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continue;
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bus.number = n;
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bus.ops = pci_root_ops;
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dev.bus = &bus;
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for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
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if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
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l != 0x0000 && l != 0xffff) {
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printk("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
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printk("PCI: Discovered peer bus %02x\n", n);
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pci_scan_bus(n, pci_root_ops, NULL);
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break;
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}
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}
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}
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/*
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* Exceptions for specific devices. Usually work-arounds for fatal design flaws.
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*/
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static void __init pci_fixup_umc_ide(struct pci_dev *d)
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{
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/*
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* UM8886BF IDE controller sets region type bits incorrectly,
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* therefore they look like memory despite of them being I/O.
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*/
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int i;
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printk("PCI: Fixing base address flags for device %s\n", pci_name(d));
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for(i=0; i<4; i++)
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d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
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}
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static void __init pci_fixup_ide_bases(struct pci_dev *d)
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{
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int i;
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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printk("PCI: IDE base address fixup for %s\n", pci_name(d));
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for(i=0; i<4; i++) {
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struct resource *r = &d->resource[i];
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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static void __init pci_fixup_ide_trash(struct pci_dev *d)
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{
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int i;
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/*
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* There exist PCI IDE controllers which have utter garbage
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* in first four base registers. Ignore that.
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*/
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printk("PCI: IDE base address trash cleared for %s\n", pci_name(d));
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for(i=0; i<4; i++)
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d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
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}
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static void __devinit pci_fixup_latency(struct pci_dev *d)
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{
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/*
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* SiS 5597 and 5598 chipsets require latency timer set to
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* at most 32 to avoid lockups.
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*/
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DBG("PCI: Setting max latency to 32\n");
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pcibios_max_latency = 32;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void __init pcibios_fixup_bus(struct pci_bus *bus)
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{
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#if 0
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printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
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#endif
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if (bus->number == 0) {
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bus->resource[0] = &pci_ioport_resource;
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bus->resource[1] = &pci_iomem_resource;
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}
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pci_read_bridge_bases(bus);
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if (bus->number == 0) {
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struct list_head *ln;
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struct pci_dev *dev;
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for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
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dev = pci_dev_b(ln);
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if (dev->devfn == 0) {
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dev->resource[0].start = 0;
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dev->resource[0].end = 0;
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}
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}
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}
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}
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/*
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* Initialization. Try all known PCI access methods. Note that we support
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* using both PCI BIOS and direct access: in such cases, we use I/O ports
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* to access config space, but we still keep BIOS order of cards to be
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* compatible with 2.0.X. This should go away some day.
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*/
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int __init pcibios_init(void)
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{
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struct pci_ops *dir = NULL;
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if (!mb93090_mb00_detected)
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return -ENXIO;
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__reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP;
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__reg_MB86943_ecs_base(1) = ((__region_CS2 + 0x01000000) >> 9) | 0x08000000;
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__reg_MB86943_ecs_base(2) = ((__region_CS2 + 0x00000000) >> 9) | 0x08000000;
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*(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000;
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*(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000;
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__reg_MB86943_sl_pci_io_base = (__region_CS2 + 0x04000000) >> 9;
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__reg_MB86943_sl_pci_mem_base = (__region_CS2 + 0x08000000) >> 9;
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__reg_MB86943_pci_sl_io_base = __region_CS2 + 0x04000000;
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__reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000;
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mb();
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/* enable PCI arbitration */
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__reg_MB86943_pci_arbiter = MB86943_PCIARB_EN;
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pci_ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
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pci_ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
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pci_ioport_resource.end += pci_ioport_resource.start;
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printk("PCI IO window: %08llx-%08llx\n",
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(unsigned long long) pci_ioport_resource.start,
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(unsigned long long) pci_ioport_resource.end);
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pci_iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
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pci_iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
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pci_iomem_resource.end += pci_iomem_resource.start;
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/* Reserve somewhere to write to flush posted writes. This is used by
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* __flush_PCI_writes() from asm/io.h to force the write FIFO in the
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* CPU-PCI bridge to flush as this doesn't happen automatically when a
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* read is performed on the MB93090 development kit motherboard.
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*/
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pci_iomem_resource.start += 0x400;
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printk("PCI MEM window: %08llx-%08llx\n",
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(unsigned long long) pci_iomem_resource.start,
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(unsigned long long) pci_iomem_resource.end);
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printk("PCI DMA memory: %08lx-%08lx\n",
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dma_coherent_mem_start, dma_coherent_mem_end);
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if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
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panic("Unable to insert PCI IOMEM resource\n");
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if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
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panic("Unable to insert PCI IOPORT resource\n");
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if (!pci_probe)
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return -ENXIO;
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dir = pci_check_direct();
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if (dir)
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pci_root_ops = dir;
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else {
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printk("PCI: No PCI bus detected\n");
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return -ENXIO;
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}
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printk("PCI: Probing PCI hardware\n");
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pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
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pcibios_irq_init();
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pcibios_fixup_peer_bridges();
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pcibios_fixup_irqs();
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pcibios_resource_survey();
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return 0;
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}
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arch_initcall(pcibios_init);
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char * __init pcibios_setup(char *str)
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{
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if (!strcmp(str, "off")) {
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pci_probe = 0;
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return NULL;
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} else if (!strncmp(str, "lastbus=", 8)) {
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pcibios_last_bus = simple_strtol(str+8, NULL, 0);
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return NULL;
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}
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return str;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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int err;
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if ((err = pci_enable_resources(dev, mask)) < 0)
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return err;
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if (!dev->msi_enabled)
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pcibios_enable_irq(dev);
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return 0;
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}
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