535 lines
14 KiB
C
535 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// rk3328 ALSA SoC Audio driver
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//
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// Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include "rk3328_codec.h"
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/*
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* volume setting
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* 0: -39dB
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* 26: 0dB
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* 31: 6dB
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* Step: 1.5dB
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*/
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#define OUT_VOLUME (0x18)
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#define RK3328_GRF_SOC_CON2 (0x0408)
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#define RK3328_GRF_SOC_CON10 (0x0428)
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#define INITIAL_FREQ (11289600)
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struct rk3328_codec_priv {
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struct regmap *regmap;
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struct gpio_desc *mute;
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struct clk *mclk;
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struct clk *pclk;
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unsigned int sclk;
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int spk_depop_time; /* msec */
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};
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static const struct reg_default rk3328_codec_reg_defaults[] = {
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{ CODEC_RESET, 0x03 },
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{ DAC_INIT_CTRL1, 0x00 },
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{ DAC_INIT_CTRL2, 0x50 },
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{ DAC_INIT_CTRL3, 0x0e },
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{ DAC_PRECHARGE_CTRL, 0x01 },
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{ DAC_PWR_CTRL, 0x00 },
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{ DAC_CLK_CTRL, 0x00 },
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{ HPMIX_CTRL, 0x00 },
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{ HPOUT_CTRL, 0x00 },
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{ HPOUTL_GAIN_CTRL, 0x00 },
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{ HPOUTR_GAIN_CTRL, 0x00 },
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{ HPOUT_POP_CTRL, 0x11 },
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};
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static int rk3328_codec_reset(struct rk3328_codec_priv *rk3328)
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{
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regmap_write(rk3328->regmap, CODEC_RESET, 0x00);
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mdelay(10);
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regmap_write(rk3328->regmap, CODEC_RESET, 0x03);
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return 0;
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}
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static int rk3328_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct rk3328_codec_priv *rk3328 =
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snd_soc_component_get_drvdata(dai->component);
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unsigned int val;
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switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
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case SND_SOC_DAIFMT_CBC_CFC:
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val = PIN_DIRECTION_IN | DAC_I2S_MODE_SLAVE;
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break;
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case SND_SOC_DAIFMT_CBP_CFP:
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val = PIN_DIRECTION_OUT | DAC_I2S_MODE_MASTER;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL1,
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PIN_DIRECTION_MASK | DAC_I2S_MODE_MASK, val);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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val = DAC_MODE_PCM;
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break;
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case SND_SOC_DAIFMT_I2S:
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val = DAC_MODE_I2S;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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val = DAC_MODE_RJM;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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val = DAC_MODE_LJM;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL2,
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DAC_MODE_MASK, val);
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return 0;
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}
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static int rk3328_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
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{
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struct rk3328_codec_priv *rk3328 =
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snd_soc_component_get_drvdata(dai->component);
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unsigned int val;
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if (mute)
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val = HPOUTL_MUTE | HPOUTR_MUTE;
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else
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val = HPOUTL_UNMUTE | HPOUTR_UNMUTE;
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regmap_update_bits(rk3328->regmap, HPOUT_CTRL,
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HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK, val);
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return 0;
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}
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static int rk3328_codec_power_on(struct rk3328_codec_priv *rk3328, int wait_ms)
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{
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regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
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DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_PRECHARGE);
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mdelay(10);
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regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
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DAC_CHARGE_CURRENT_ALL_MASK,
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DAC_CHARGE_CURRENT_ALL_ON);
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mdelay(wait_ms);
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return 0;
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}
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static int rk3328_codec_power_off(struct rk3328_codec_priv *rk3328, int wait_ms)
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{
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regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
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DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_DISCHARGE);
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mdelay(10);
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regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
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DAC_CHARGE_CURRENT_ALL_MASK,
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DAC_CHARGE_CURRENT_ALL_ON);
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mdelay(wait_ms);
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return 0;
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}
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static const struct rk3328_reg_msk_val playback_open_list[] = {
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{ DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_ON },
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{ DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
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DACL_PATH_REFV_ON | DACR_PATH_REFV_ON },
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{ DAC_PWR_CTRL, HPOUTL_ZERO_CROSSING_MASK | HPOUTR_ZERO_CROSSING_MASK,
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HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON },
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{ HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
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HPOUTR_POP_WORK | HPOUTL_POP_WORK },
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{ HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_EN | HPMIXR_EN },
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{ HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
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HPMIXL_INIT_EN | HPMIXR_INIT_EN },
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{ HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_EN | HPOUTR_EN },
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{ HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
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HPOUTL_INIT_EN | HPOUTR_INIT_EN },
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{ DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
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DACL_REFV_ON | DACR_REFV_ON },
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{ DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
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DACL_CLK_ON | DACR_CLK_ON },
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{ DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_ON | DACR_ON },
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{ DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
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DACL_INIT_ON | DACR_INIT_ON },
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{ DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
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DACL_SELECT | DACR_SELECT },
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{ HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
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HPMIXL_INIT2_EN | HPMIXR_INIT2_EN },
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{ HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
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HPOUTL_UNMUTE | HPOUTR_UNMUTE },
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};
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static int rk3328_codec_open_playback(struct rk3328_codec_priv *rk3328)
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{
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int i;
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regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
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DAC_CHARGE_CURRENT_ALL_MASK,
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DAC_CHARGE_CURRENT_I);
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for (i = 0; i < ARRAY_SIZE(playback_open_list); i++) {
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regmap_update_bits(rk3328->regmap,
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playback_open_list[i].reg,
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playback_open_list[i].msk,
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playback_open_list[i].val);
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mdelay(1);
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}
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msleep(rk3328->spk_depop_time);
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gpiod_set_value(rk3328->mute, 0);
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regmap_update_bits(rk3328->regmap, HPOUTL_GAIN_CTRL,
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HPOUTL_GAIN_MASK, OUT_VOLUME);
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regmap_update_bits(rk3328->regmap, HPOUTR_GAIN_CTRL,
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HPOUTR_GAIN_MASK, OUT_VOLUME);
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return 0;
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}
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static const struct rk3328_reg_msk_val playback_close_list[] = {
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{ HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
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HPMIXL_INIT2_DIS | HPMIXR_INIT2_DIS },
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{ DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
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DACL_UNSELECT | DACR_UNSELECT },
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{ HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
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HPOUTL_MUTE | HPOUTR_MUTE },
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{ HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
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HPOUTL_INIT_DIS | HPOUTR_INIT_DIS },
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{ HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_DIS | HPOUTR_DIS },
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{ HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_DIS | HPMIXR_DIS },
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{ DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_OFF | DACR_OFF },
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{ DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
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DACL_CLK_OFF | DACR_CLK_OFF },
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{ DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
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DACL_REFV_OFF | DACR_REFV_OFF },
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{ HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
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HPOUTR_POP_XCHARGE | HPOUTL_POP_XCHARGE },
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{ DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
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DACL_PATH_REFV_OFF | DACR_PATH_REFV_OFF },
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{ DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_OFF },
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{ HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
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HPMIXL_INIT_DIS | HPMIXR_INIT_DIS },
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{ DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
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DACL_INIT_OFF | DACR_INIT_OFF },
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};
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static int rk3328_codec_close_playback(struct rk3328_codec_priv *rk3328)
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{
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size_t i;
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gpiod_set_value(rk3328->mute, 1);
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regmap_update_bits(rk3328->regmap, HPOUTL_GAIN_CTRL,
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HPOUTL_GAIN_MASK, 0);
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regmap_update_bits(rk3328->regmap, HPOUTR_GAIN_CTRL,
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HPOUTR_GAIN_MASK, 0);
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for (i = 0; i < ARRAY_SIZE(playback_close_list); i++) {
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regmap_update_bits(rk3328->regmap,
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playback_close_list[i].reg,
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playback_close_list[i].msk,
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playback_close_list[i].val);
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mdelay(1);
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}
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/* Workaround for silence when changed Fs 48 -> 44.1kHz */
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rk3328_codec_reset(rk3328);
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regmap_update_bits(rk3328->regmap, DAC_PRECHARGE_CTRL,
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DAC_CHARGE_CURRENT_ALL_MASK,
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DAC_CHARGE_CURRENT_ALL_ON);
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return 0;
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}
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static int rk3328_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct rk3328_codec_priv *rk3328 =
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snd_soc_component_get_drvdata(dai->component);
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unsigned int val = 0;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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val = DAC_VDL_16BITS;
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break;
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case SNDRV_PCM_FORMAT_S20_3LE:
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val = DAC_VDL_20BITS;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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val = DAC_VDL_24BITS;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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val = DAC_VDL_32BITS;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL2, DAC_VDL_MASK, val);
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val = DAC_WL_32BITS | DAC_RST_DIS;
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regmap_update_bits(rk3328->regmap, DAC_INIT_CTRL3,
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DAC_WL_MASK | DAC_RST_MASK, val);
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return 0;
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}
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static int rk3328_pcm_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct rk3328_codec_priv *rk3328 =
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snd_soc_component_get_drvdata(dai->component);
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return rk3328_codec_open_playback(rk3328);
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}
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static void rk3328_pcm_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct rk3328_codec_priv *rk3328 =
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snd_soc_component_get_drvdata(dai->component);
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rk3328_codec_close_playback(rk3328);
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}
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static const struct snd_soc_dai_ops rk3328_dai_ops = {
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.hw_params = rk3328_hw_params,
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.set_fmt = rk3328_set_dai_fmt,
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.mute_stream = rk3328_mute_stream,
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.startup = rk3328_pcm_startup,
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.shutdown = rk3328_pcm_shutdown,
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.no_capture_mute = 1,
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};
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static struct snd_soc_dai_driver rk3328_dai[] = {
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{
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.name = "rk3328-hifi",
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.id = RK3328_HIFI,
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.playback = {
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.stream_name = "HIFI Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = (SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S20_3LE |
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE),
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},
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.capture = {
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.stream_name = "HIFI Capture",
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.channels_min = 2,
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.channels_max = 8,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = (SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S20_3LE |
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SNDRV_PCM_FMTBIT_S24_LE |
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SNDRV_PCM_FMTBIT_S32_LE),
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},
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.ops = &rk3328_dai_ops,
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},
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};
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static int rk3328_codec_probe(struct snd_soc_component *component)
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{
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struct rk3328_codec_priv *rk3328 =
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snd_soc_component_get_drvdata(component);
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rk3328_codec_reset(rk3328);
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rk3328_codec_power_on(rk3328, 0);
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return 0;
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}
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static void rk3328_codec_remove(struct snd_soc_component *component)
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{
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struct rk3328_codec_priv *rk3328 =
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snd_soc_component_get_drvdata(component);
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rk3328_codec_close_playback(rk3328);
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rk3328_codec_power_off(rk3328, 0);
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}
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static const struct snd_soc_component_driver soc_codec_rk3328 = {
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.probe = rk3328_codec_probe,
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.remove = rk3328_codec_remove,
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};
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static bool rk3328_codec_write_read_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CODEC_RESET:
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case DAC_INIT_CTRL1:
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case DAC_INIT_CTRL2:
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case DAC_INIT_CTRL3:
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case DAC_PRECHARGE_CTRL:
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case DAC_PWR_CTRL:
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case DAC_CLK_CTRL:
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case HPMIX_CTRL:
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case DAC_SELECT:
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case HPOUT_CTRL:
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case HPOUTL_GAIN_CTRL:
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case HPOUTR_GAIN_CTRL:
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case HPOUT_POP_CTRL:
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return true;
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default:
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return false;
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}
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}
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static bool rk3328_codec_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case CODEC_RESET:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config rk3328_codec_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = HPOUT_POP_CTRL,
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.writeable_reg = rk3328_codec_write_read_reg,
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.readable_reg = rk3328_codec_write_read_reg,
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.volatile_reg = rk3328_codec_volatile_reg,
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.reg_defaults = rk3328_codec_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(rk3328_codec_reg_defaults),
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.cache_type = REGCACHE_FLAT,
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};
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static int rk3328_platform_probe(struct platform_device *pdev)
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{
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struct device_node *rk3328_np = pdev->dev.of_node;
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struct rk3328_codec_priv *rk3328;
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struct regmap *grf;
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void __iomem *base;
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int ret = 0;
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rk3328 = devm_kzalloc(&pdev->dev, sizeof(*rk3328), GFP_KERNEL);
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if (!rk3328)
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return -ENOMEM;
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grf = syscon_regmap_lookup_by_phandle(rk3328_np,
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"rockchip,grf");
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if (IS_ERR(grf)) {
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dev_err(&pdev->dev, "missing 'rockchip,grf'\n");
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return PTR_ERR(grf);
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}
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/* enable i2s_acodec_en */
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regmap_write(grf, RK3328_GRF_SOC_CON2,
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(BIT(14) << 16 | BIT(14)));
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ret = of_property_read_u32(rk3328_np, "spk-depop-time-ms",
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&rk3328->spk_depop_time);
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if (ret < 0) {
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dev_info(&pdev->dev, "spk_depop_time use default value.\n");
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rk3328->spk_depop_time = 200;
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}
|
|
|
|
rk3328->mute = gpiod_get_optional(&pdev->dev, "mute", GPIOD_OUT_HIGH);
|
|
if (IS_ERR(rk3328->mute))
|
|
return PTR_ERR(rk3328->mute);
|
|
/*
|
|
* Rock64 is the only supported platform to have widely relied on
|
|
* this; if we do happen to come across an old DTB, just leave the
|
|
* external mute forced off.
|
|
*/
|
|
if (!rk3328->mute && of_machine_is_compatible("pine64,rock64")) {
|
|
dev_warn(&pdev->dev, "assuming implicit control of GPIO_MUTE; update devicetree if possible\n");
|
|
regmap_write(grf, RK3328_GRF_SOC_CON10, BIT(17) | BIT(1));
|
|
}
|
|
|
|
rk3328->mclk = devm_clk_get(&pdev->dev, "mclk");
|
|
if (IS_ERR(rk3328->mclk))
|
|
return PTR_ERR(rk3328->mclk);
|
|
|
|
ret = clk_prepare_enable(rk3328->mclk);
|
|
if (ret)
|
|
return ret;
|
|
clk_set_rate(rk3328->mclk, INITIAL_FREQ);
|
|
|
|
rk3328->pclk = devm_clk_get(&pdev->dev, "pclk");
|
|
if (IS_ERR(rk3328->pclk)) {
|
|
dev_err(&pdev->dev, "can't get acodec pclk\n");
|
|
ret = PTR_ERR(rk3328->pclk);
|
|
goto err_unprepare_mclk;
|
|
}
|
|
|
|
ret = clk_prepare_enable(rk3328->pclk);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to enable acodec pclk\n");
|
|
goto err_unprepare_mclk;
|
|
}
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base)) {
|
|
ret = PTR_ERR(base);
|
|
goto err_unprepare_pclk;
|
|
}
|
|
|
|
rk3328->regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
|
&rk3328_codec_regmap_config);
|
|
if (IS_ERR(rk3328->regmap)) {
|
|
ret = PTR_ERR(rk3328->regmap);
|
|
goto err_unprepare_pclk;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, rk3328);
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_rk3328,
|
|
rk3328_dai,
|
|
ARRAY_SIZE(rk3328_dai));
|
|
if (ret)
|
|
goto err_unprepare_pclk;
|
|
|
|
return 0;
|
|
|
|
err_unprepare_pclk:
|
|
clk_disable_unprepare(rk3328->pclk);
|
|
|
|
err_unprepare_mclk:
|
|
clk_disable_unprepare(rk3328->mclk);
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id rk3328_codec_of_match[] __maybe_unused = {
|
|
{ .compatible = "rockchip,rk3328-codec", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rk3328_codec_of_match);
|
|
|
|
static struct platform_driver rk3328_codec_driver = {
|
|
.driver = {
|
|
.name = "rk3328-codec",
|
|
.of_match_table = of_match_ptr(rk3328_codec_of_match),
|
|
},
|
|
.probe = rk3328_platform_probe,
|
|
};
|
|
module_platform_driver(rk3328_codec_driver);
|
|
|
|
MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
|
|
MODULE_DESCRIPTION("ASoC rk3328 codec driver");
|
|
MODULE_LICENSE("GPL v2");
|