423 lines
11 KiB
C
423 lines
11 KiB
C
/*
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* Copyright (c) 2012 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/export.h>
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#include "ath9k.h"
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#include "reg.h"
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#include "hw-ops.h"
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const char *ath9k_hw_wow_event_to_string(u32 wow_event)
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{
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if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
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return "Magic pattern";
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if (wow_event & AH_WOW_USER_PATTERN_EN)
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return "User pattern";
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if (wow_event & AH_WOW_LINK_CHANGE)
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return "Link change";
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if (wow_event & AH_WOW_BEACON_MISS)
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return "Beacon miss";
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return "unknown reason";
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}
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EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
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static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
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/* set rx disable bit */
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REG_WRITE(ah, AR_CR, AR_CR_RXD);
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if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
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ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
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REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
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return;
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}
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REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
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}
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static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
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u32 ctl[13] = {0};
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u32 data_word[KAL_NUM_DATA_WORDS];
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u8 i;
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u32 wow_ka_data_word0;
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memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
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memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
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/* set the transmit buffer */
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ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
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ctl[1] = 0;
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ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */
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ctl[4] = 0;
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ctl[7] = (ah->txchainmask) << 2;
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ctl[2] = 0xf << 16; /* tx_tries 0 */
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for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
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REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
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REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
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data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
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(KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
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data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
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(ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
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data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
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(ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
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data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
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(sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
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data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
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(ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
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data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
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if (AR_SREV_9462_20(ah)) {
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/* AR9462 2.0 has an extra descriptor word (time based
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* discard) compared to other chips */
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REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
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wow_ka_data_word0 = AR_WOW_TXBUF(13);
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} else {
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wow_ka_data_word0 = AR_WOW_TXBUF(12);
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}
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for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
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REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
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}
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void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
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u8 *user_mask, int pattern_count,
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int pattern_len)
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{
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int i;
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u32 pattern_val, mask_val;
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u32 set, clr;
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/* FIXME: should check count by querying the hardware capability */
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if (pattern_count >= MAX_NUM_PATTERN)
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return;
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REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
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/* set the registers for pattern */
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for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
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memcpy(&pattern_val, user_pattern, 4);
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REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
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pattern_val);
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user_pattern += 4;
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}
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/* set the registers for mask */
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for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
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memcpy(&mask_val, user_mask, 4);
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REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
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user_mask += 4;
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}
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/* set the pattern length to be matched
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*
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* AR_WOW_LENGTH1_REG1
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* bit 31:24 pattern 0 length
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* bit 23:16 pattern 1 length
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* bit 15:8 pattern 2 length
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* bit 7:0 pattern 3 length
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*
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* AR_WOW_LENGTH1_REG2
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* bit 31:24 pattern 4 length
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* bit 23:16 pattern 5 length
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* bit 15:8 pattern 6 length
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* bit 7:0 pattern 7 length
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*
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* the below logic writes out the new
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* pattern length for the corresponding
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* pattern_count, while masking out the
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* other fields
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*/
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ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
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if (pattern_count < 4) {
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/* Pattern 0-3 uses AR_WOW_LENGTH1 register */
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set = (pattern_len & AR_WOW_LENGTH_MAX) <<
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AR_WOW_LEN1_SHIFT(pattern_count);
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clr = AR_WOW_LENGTH1_MASK(pattern_count);
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REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
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} else {
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/* Pattern 4-7 uses AR_WOW_LENGTH2 register */
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set = (pattern_len & AR_WOW_LENGTH_MAX) <<
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AR_WOW_LEN2_SHIFT(pattern_count);
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clr = AR_WOW_LENGTH2_MASK(pattern_count);
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REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
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}
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}
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EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
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u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
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{
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u32 wow_status = 0;
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u32 val = 0, rval;
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/*
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* read the WoW status register to know
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* the wakeup reason
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*/
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rval = REG_READ(ah, AR_WOW_PATTERN);
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val = AR_WOW_STATUS(rval);
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/*
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* mask only the WoW events that we have enabled. Sometimes
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* we have spurious WoW events from the AR_WOW_PATTERN
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* register. This mask will clean it up.
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*/
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val &= ah->wow_event_mask;
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if (val) {
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if (val & AR_WOW_MAGIC_PAT_FOUND)
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wow_status |= AH_WOW_MAGIC_PATTERN_EN;
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if (AR_WOW_PATTERN_FOUND(val))
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wow_status |= AH_WOW_USER_PATTERN_EN;
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if (val & AR_WOW_KEEP_ALIVE_FAIL)
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wow_status |= AH_WOW_LINK_CHANGE;
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if (val & AR_WOW_BEACON_FAIL)
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wow_status |= AH_WOW_BEACON_MISS;
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}
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/*
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* set and clear WOW_PME_CLEAR registers for the chip to
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* generate next wow signal.
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* disable D3 before accessing other registers ?
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*/
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/* do we need to check the bit value 0x01000000 (7-10) ?? */
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REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
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AR_PMCTRL_PWR_STATE_D1D3);
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/*
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* clear all events
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*/
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REG_WRITE(ah, AR_WOW_PATTERN,
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AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
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/*
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* restore the beacon threshold to init value
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*/
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REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
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/*
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* Restore the way the PCI-E reset, Power-On-Reset, external
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* PCIE_POR_SHORT pins are tied to its original value.
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* Previously just before WoW sleep, we untie the PCI-E
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* reset to our Chip's Power On Reset so that any PCI-E
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* reset from the bus will not reset our chip
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*/
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if (ah->is_pciexpress)
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ath9k_hw_configpcipowersave(ah, false);
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ah->wow_event_mask = 0;
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return wow_status;
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}
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EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
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void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
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{
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u32 wow_event_mask;
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u32 set, clr;
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/*
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* wow_event_mask is a mask to the AR_WOW_PATTERN register to
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* indicate which WoW events we have enabled. The WoW events
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* are from the 'pattern_enable' in this function and
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* 'pattern_count' of ath9k_hw_wow_apply_pattern()
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*/
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wow_event_mask = ah->wow_event_mask;
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/*
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* Untie Power-on-Reset from the PCI-E-Reset. When we are in
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* WOW sleep, we do want the Reset from the PCI-E to disturb
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* our hw state
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*/
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if (ah->is_pciexpress) {
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/*
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* we need to untie the internal POR (power-on-reset)
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* to the external PCI-E reset. We also need to tie
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* the PCI-E Phy reset to the PCI-E reset.
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*/
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set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
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clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
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REG_RMW(ah, AR_WA, set, clr);
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}
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/*
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* set the power states appropriately and enable PME
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*/
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set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
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AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
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/*
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* set and clear WOW_PME_CLEAR registers for the chip
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* to generate next wow signal.
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*/
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REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
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clr = AR_PMCTRL_WOW_PME_CLR;
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REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
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/*
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* Setup for:
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* - beacon misses
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* - magic pattern
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* - keep alive timeout
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* - pattern matching
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*/
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/*
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* Program default values for pattern backoff, aifs/slot/KAL count,
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* beacon miss timeout, KAL timeout, etc.
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*/
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set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
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REG_SET_BIT(ah, AR_WOW_PATTERN, set);
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set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
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AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
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AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
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REG_SET_BIT(ah, AR_WOW_COUNT, set);
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if (pattern_enable & AH_WOW_BEACON_MISS)
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set = AR_WOW_BEACON_TIMO;
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/* We are not using beacon miss, program a large value */
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else
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set = AR_WOW_BEACON_TIMO_MAX;
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REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
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/*
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* Keep alive timo in ms except AR9280
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*/
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if (!pattern_enable)
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set = AR_WOW_KEEP_ALIVE_NEVER;
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else
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set = KAL_TIMEOUT * 32;
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REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
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/*
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* Keep alive delay in us. based on 'power on clock',
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* therefore in usec
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*/
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set = KAL_DELAY * 1000;
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REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
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/*
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* Create keep alive pattern to respond to beacons
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*/
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ath9k_wow_create_keep_alive_pattern(ah);
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/*
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* Configure MAC WoW Registers
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*/
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set = 0;
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/* Send keep alive timeouts anyway */
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clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
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if (pattern_enable & AH_WOW_LINK_CHANGE)
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wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
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else
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set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
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set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
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REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
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/*
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* we are relying on a bmiss failure. ensure we have
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* enough threshold to prevent false positives
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*/
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REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
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AR_WOW_BMISSTHRESHOLD);
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set = 0;
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clr = 0;
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if (pattern_enable & AH_WOW_BEACON_MISS) {
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set = AR_WOW_BEACON_FAIL_EN;
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wow_event_mask |= AR_WOW_BEACON_FAIL;
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} else {
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clr = AR_WOW_BEACON_FAIL_EN;
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}
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REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
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set = 0;
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clr = 0;
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/*
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* Enable the magic packet registers
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*/
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if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
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set = AR_WOW_MAGIC_EN;
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wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
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} else {
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clr = AR_WOW_MAGIC_EN;
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}
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set |= AR_WOW_MAC_INTR_EN;
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REG_RMW(ah, AR_WOW_PATTERN, set, clr);
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REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
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AR_WOW_PATTERN_SUPPORTED);
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/*
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* Set the power states appropriately and enable PME
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*/
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clr = 0;
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set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
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AR_PMCTRL_PWR_PM_CTRL_ENA;
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clr = AR_PCIE_PM_CTRL_ENA;
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REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
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/*
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* this is needed to prevent the chip waking up
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* the host within 3-4 seconds with certain
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* platform/BIOS. The fix is to enable
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* D1 & D3 to match original definition and
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* also match the OTP value. Anyway this
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* is more related to SW WOW.
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*/
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clr = AR_PMCTRL_PWR_STATE_D1D3;
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REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
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set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
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REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
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REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
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/* to bring down WOW power low margin */
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set = BIT(13);
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REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
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/* HW WoW */
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clr = BIT(5);
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REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
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ath9k_hw_set_powermode_wow_sleep(ah);
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ah->wow_event_mask = wow_event_mask;
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}
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EXPORT_SYMBOL(ath9k_hw_wow_enable);
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