373 lines
9.4 KiB
C
373 lines
9.4 KiB
C
/*
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* DaVinci timer subsystem
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/spinlock.h>
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/errno.h>
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#include <asm/arch/io.h>
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static struct clock_event_device clockevent_davinci;
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#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
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#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
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#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
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enum {
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T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS,
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};
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#define IS_TIMER1(id) (id & 0x2)
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#define IS_TIMER0(id) (!IS_TIMER1(id))
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#define IS_TIMER_TOP(id) ((id & 0x1))
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#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
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static int timer_irqs[NUM_TIMERS] = {
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IRQ_TINT0_TINT12,
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IRQ_TINT0_TINT34,
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IRQ_TINT1_TINT12,
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IRQ_TINT1_TINT34,
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};
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/*
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* This driver configures the 2 64-bit count-up timers as 4 independent
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* 32-bit count-up timers used as follows:
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*
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* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
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* T0_TOP: Timer 0, top : clocksource for generic timekeeping
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* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
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* T1_TOP: Timer 1, top : <unused>
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*/
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#define TID_CLOCKEVENT T0_BOT
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#define TID_CLOCKSOURCE T0_TOP
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/* Timer register offsets */
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#define PID12 0x0
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#define TIM12 0x10
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#define TIM34 0x14
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#define PRD12 0x18
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#define PRD34 0x1c
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#define TCR 0x20
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#define TGCR 0x24
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#define WDTCR 0x28
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/* Timer register bitfields */
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#define TCR_ENAMODE_DISABLE 0x0
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#define TCR_ENAMODE_ONESHOT 0x1
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#define TCR_ENAMODE_PERIODIC 0x2
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#define TCR_ENAMODE_MASK 0x3
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#define TGCR_TIMMODE_SHIFT 2
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#define TGCR_TIMMODE_64BIT_GP 0x0
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#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
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#define TGCR_TIMMODE_64BIT_WDOG 0x2
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#define TGCR_TIMMODE_32BIT_CHAINED 0x3
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#define TGCR_TIM12RS_SHIFT 0
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#define TGCR_TIM34RS_SHIFT 1
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#define TGCR_RESET 0x0
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#define TGCR_UNRESET 0x1
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#define TGCR_RESET_MASK 0x3
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#define WDTCR_WDEN_SHIFT 14
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#define WDTCR_WDEN_DISABLE 0x0
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#define WDTCR_WDEN_ENABLE 0x1
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#define WDTCR_WDKEY_SHIFT 16
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#define WDTCR_WDKEY_SEQ0 0xa5c6
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#define WDTCR_WDKEY_SEQ1 0xda7e
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struct timer_s {
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char *name;
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unsigned int id;
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unsigned long period;
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unsigned long opts;
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unsigned long reg_base;
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unsigned long tim_reg;
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unsigned long prd_reg;
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unsigned long enamode_shift;
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struct irqaction irqaction;
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};
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static struct timer_s timers[];
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/* values for 'opts' field of struct timer_s */
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#define TIMER_OPTS_DISABLED 0x00
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#define TIMER_OPTS_ONESHOT 0x01
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#define TIMER_OPTS_PERIODIC 0x02
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static int timer32_config(struct timer_s *t)
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{
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u32 tcr = davinci_readl(t->reg_base + TCR);
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/* disable timer */
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tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
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davinci_writel(tcr, t->reg_base + TCR);
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/* reset counter to zero, set new period */
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davinci_writel(0, t->tim_reg);
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davinci_writel(t->period, t->prd_reg);
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/* Set enable mode */
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if (t->opts & TIMER_OPTS_ONESHOT) {
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tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
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} else if (t->opts & TIMER_OPTS_PERIODIC) {
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tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
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}
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davinci_writel(tcr, t->reg_base + TCR);
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return 0;
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}
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static inline u32 timer32_read(struct timer_s *t)
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{
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return davinci_readl(t->tim_reg);
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_davinci;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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/* called when 32-bit counter wraps */
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static irqreturn_t freerun_interrupt(int irq, void *dev_id)
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{
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return IRQ_HANDLED;
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}
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static struct timer_s timers[] = {
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[TID_CLOCKEVENT] = {
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.name = "clockevent",
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.opts = TIMER_OPTS_DISABLED,
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.irqaction = {
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = timer_interrupt,
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}
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},
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[TID_CLOCKSOURCE] = {
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.name = "free-run counter",
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.period = ~0,
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.opts = TIMER_OPTS_PERIODIC,
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.irqaction = {
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = freerun_interrupt,
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}
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},
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};
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static void __init timer_init(void)
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{
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u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
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int i;
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/* Global init of each 64-bit timer as a whole */
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for(i=0; i<2; i++) {
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u32 tgcr, base = bases[i];
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/* Disabled, Internal clock source */
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davinci_writel(0, base + TCR);
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/* reset both timers, no pre-scaler for timer34 */
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tgcr = 0;
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davinci_writel(tgcr, base + TGCR);
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/* Set both timers to unchained 32-bit */
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tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
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davinci_writel(tgcr, base + TGCR);
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/* Unreset timers */
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tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
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(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
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davinci_writel(tgcr, base + TGCR);
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/* Init both counters to zero */
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davinci_writel(0, base + TIM12);
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davinci_writel(0, base + TIM34);
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}
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/* Init of each timer as a 32-bit timer */
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for (i=0; i< ARRAY_SIZE(timers); i++) {
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struct timer_s *t = &timers[i];
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if (t->name) {
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t->id = i;
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t->reg_base = (IS_TIMER1(t->id) ?
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DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE);
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if (IS_TIMER_BOT(t->id)) {
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t->enamode_shift = 6;
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t->tim_reg = t->reg_base + TIM12;
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t->prd_reg = t->reg_base + PRD12;
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} else {
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t->enamode_shift = 22;
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t->tim_reg = t->reg_base + TIM34;
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t->prd_reg = t->reg_base + PRD34;
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}
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/* Register interrupt */
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t->irqaction.name = t->name;
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t->irqaction.dev_id = (void *)t;
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if (t->irqaction.handler != NULL) {
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setup_irq(timer_irqs[t->id], &t->irqaction);
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}
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timer32_config(&timers[i]);
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}
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}
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}
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/*
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* clocksource
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*/
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static cycle_t read_cycles(void)
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{
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struct timer_s *t = &timers[TID_CLOCKSOURCE];
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return (cycles_t)timer32_read(t);
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}
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static struct clocksource clocksource_davinci = {
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.name = "timer0_1",
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.rating = 300,
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.read = read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 24,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* clockevent
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*/
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static int davinci_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct timer_s *t = &timers[TID_CLOCKEVENT];
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t->period = cycles;
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timer32_config(t);
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return 0;
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}
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static void davinci_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct timer_s *t = &timers[TID_CLOCKEVENT];
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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t->period = CLOCK_TICK_RATE / (HZ);
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t->opts = TIMER_OPTS_PERIODIC;
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timer32_config(t);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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t->opts = TIMER_OPTS_ONESHOT;
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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t->opts = TIMER_OPTS_DISABLED;
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break;
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}
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}
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static struct clock_event_device clockevent_davinci = {
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.name = "timer0_0",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_next_event = davinci_set_next_event,
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.set_mode = davinci_set_mode,
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};
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static void __init davinci_timer_init(void)
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{
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static char err[] __initdata = KERN_ERR
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"%s: can't register clocksource!\n";
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/* init timer hw */
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timer_init();
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/* setup clocksource */
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clocksource_davinci.mult =
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clocksource_khz2mult(CLOCK_TICK_RATE/1000,
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clocksource_davinci.shift);
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if (clocksource_register(&clocksource_davinci))
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printk(err, clocksource_davinci.name);
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/* setup clockevent */
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clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
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clockevent_davinci.shift);
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clockevent_davinci.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
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clockevent_davinci.min_delta_ns =
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clockevent_delta2ns(1, &clockevent_davinci);
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clockevent_davinci.cpumask = cpumask_of_cpu(0);
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clockevents_register_device(&clockevent_davinci);
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}
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struct sys_timer davinci_timer = {
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.init = davinci_timer_init,
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};
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/* reset board using watchdog timer */
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void davinci_watchdog_reset(void) {
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u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE;
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/* disable, internal clock source */
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davinci_writel(0, base + TCR);
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/* reset timer, set mode to 64-bit watchdog, and unreset */
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tgcr = 0;
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davinci_writel(tgcr, base + TCR);
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tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
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tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
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(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
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davinci_writel(tgcr, base + TCR);
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/* clear counter and period regs */
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davinci_writel(0, base + TIM12);
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davinci_writel(0, base + TIM34);
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davinci_writel(0, base + PRD12);
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davinci_writel(0, base + PRD34);
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/* enable */
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wdtcr = davinci_readl(base + WDTCR);
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wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
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davinci_writel(wdtcr, base + WDTCR);
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/* put watchdog in pre-active state */
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wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
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(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
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davinci_writel(wdtcr, base + WDTCR);
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/* put watchdog in active state */
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wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
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(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
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davinci_writel(wdtcr, base + WDTCR);
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/* write an invalid value to the WDKEY field to trigger
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* a watchdog reset */
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wdtcr = 0x00004000;
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davinci_writel(wdtcr, base + WDTCR);
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}
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