1346 lines
30 KiB
ArmAsm
1346 lines
30 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*
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* Derived from book3s_rmhandlers.S and other files, which are:
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*
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* Copyright SUSE Linux Products GmbH 2009
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#include <asm/ppc_asm.h>
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#include <asm/kvm_asm.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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#include <asm/exception-64s.h>
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/*****************************************************************************
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* *
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* Real Mode handlers that need to be in the linear mapping *
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* *
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****************************************************************************/
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.globl kvmppc_skip_interrupt
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kvmppc_skip_interrupt:
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mfspr r13,SPRN_SRR0
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addi r13,r13,4
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mtspr SPRN_SRR0,r13
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GET_SCRATCH0(r13)
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rfid
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b .
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.globl kvmppc_skip_Hinterrupt
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kvmppc_skip_Hinterrupt:
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mfspr r13,SPRN_HSRR0
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addi r13,r13,4
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mtspr SPRN_HSRR0,r13
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GET_SCRATCH0(r13)
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hrfid
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b .
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/*
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* Call kvmppc_handler_trampoline_enter in real mode.
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* Must be called with interrupts hard-disabled.
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*
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* Input Registers:
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*
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* LR = return address to continue at after eventually re-enabling MMU
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*/
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_GLOBAL(kvmppc_hv_entry_trampoline)
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mfmsr r10
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LOAD_REG_ADDR(r5, kvmppc_hv_entry)
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li r0,MSR_RI
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andc r0,r10,r0
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li r6,MSR_IR | MSR_DR
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andc r6,r10,r6
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mtmsrd r0,1 /* clear RI in MSR */
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mtsrr0 r5
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mtsrr1 r6
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RFI
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#define ULONG_SIZE 8
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#define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
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/******************************************************************************
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* *
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* Entry code *
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* *
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*****************************************************************************/
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#define XICS_XIRR 4
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#define XICS_QIRR 0xc
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/*
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* We come in here when wakened from nap mode on a secondary hw thread.
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* Relocation is off and most register values are lost.
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* r13 points to the PACA.
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*/
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.globl kvm_start_guest
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kvm_start_guest:
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ld r1,PACAEMERGSP(r13)
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subi r1,r1,STACK_FRAME_OVERHEAD
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/* get vcpu pointer */
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ld r4, HSTATE_KVM_VCPU(r13)
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/* We got here with an IPI; clear it */
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ld r5, HSTATE_XICS_PHYS(r13)
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li r0, 0xff
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li r6, XICS_QIRR
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li r7, XICS_XIRR
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lwzcix r8, r5, r7 /* ack the interrupt */
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sync
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stbcix r0, r5, r6 /* clear it */
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stwcix r8, r5, r7 /* EOI it */
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.global kvmppc_hv_entry
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kvmppc_hv_entry:
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/* Required state:
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*
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* R4 = vcpu pointer
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* MSR = ~IR|DR
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* R13 = PACA
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* R1 = host R1
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* all other volatile GPRS = free
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*/
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mflr r0
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std r0, HSTATE_VMHANDLER(r13)
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ld r14, VCPU_GPR(r14)(r4)
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ld r15, VCPU_GPR(r15)(r4)
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ld r16, VCPU_GPR(r16)(r4)
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ld r17, VCPU_GPR(r17)(r4)
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ld r18, VCPU_GPR(r18)(r4)
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ld r19, VCPU_GPR(r19)(r4)
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ld r20, VCPU_GPR(r20)(r4)
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ld r21, VCPU_GPR(r21)(r4)
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ld r22, VCPU_GPR(r22)(r4)
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ld r23, VCPU_GPR(r23)(r4)
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ld r24, VCPU_GPR(r24)(r4)
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ld r25, VCPU_GPR(r25)(r4)
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ld r26, VCPU_GPR(r26)(r4)
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ld r27, VCPU_GPR(r27)(r4)
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ld r28, VCPU_GPR(r28)(r4)
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ld r29, VCPU_GPR(r29)(r4)
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ld r30, VCPU_GPR(r30)(r4)
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ld r31, VCPU_GPR(r31)(r4)
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/* Load guest PMU registers */
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/* R4 is live here (vcpu pointer) */
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li r3, 1
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sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
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mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
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isync
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lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
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lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
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lwz r6, VCPU_PMC + 8(r4)
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lwz r7, VCPU_PMC + 12(r4)
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lwz r8, VCPU_PMC + 16(r4)
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lwz r9, VCPU_PMC + 20(r4)
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BEGIN_FTR_SECTION
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lwz r10, VCPU_PMC + 24(r4)
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lwz r11, VCPU_PMC + 28(r4)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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mtspr SPRN_PMC1, r3
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mtspr SPRN_PMC2, r5
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mtspr SPRN_PMC3, r6
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mtspr SPRN_PMC4, r7
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mtspr SPRN_PMC5, r8
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mtspr SPRN_PMC6, r9
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BEGIN_FTR_SECTION
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mtspr SPRN_PMC7, r10
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mtspr SPRN_PMC8, r11
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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ld r3, VCPU_MMCR(r4)
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ld r5, VCPU_MMCR + 8(r4)
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ld r6, VCPU_MMCR + 16(r4)
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mtspr SPRN_MMCR1, r5
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mtspr SPRN_MMCRA, r6
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mtspr SPRN_MMCR0, r3
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isync
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/* Load up FP, VMX and VSX registers */
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bl kvmppc_load_fp
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BEGIN_FTR_SECTION
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/* Switch DSCR to guest value */
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ld r5, VCPU_DSCR(r4)
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mtspr SPRN_DSCR, r5
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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/*
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* Set the decrementer to the guest decrementer.
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*/
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ld r8,VCPU_DEC_EXPIRES(r4)
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mftb r7
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subf r3,r7,r8
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mtspr SPRN_DEC,r3
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stw r3,VCPU_DEC(r4)
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ld r5, VCPU_SPRG0(r4)
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ld r6, VCPU_SPRG1(r4)
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ld r7, VCPU_SPRG2(r4)
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ld r8, VCPU_SPRG3(r4)
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mtspr SPRN_SPRG0, r5
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mtspr SPRN_SPRG1, r6
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mtspr SPRN_SPRG2, r7
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mtspr SPRN_SPRG3, r8
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/* Save R1 in the PACA */
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std r1, HSTATE_HOST_R1(r13)
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/* Increment yield count if they have a VPA */
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ld r3, VCPU_VPA(r4)
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cmpdi r3, 0
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beq 25f
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lwz r5, LPPACA_YIELDCOUNT(r3)
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addi r5, r5, 1
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stw r5, LPPACA_YIELDCOUNT(r3)
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25:
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/* Load up DAR and DSISR */
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ld r5, VCPU_DAR(r4)
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lwz r6, VCPU_DSISR(r4)
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mtspr SPRN_DAR, r5
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mtspr SPRN_DSISR, r6
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/* Set partition DABR */
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li r5,3
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ld r6,VCPU_DABR(r4)
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mtspr SPRN_DABRX,r5
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mtspr SPRN_DABR,r6
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BEGIN_FTR_SECTION
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/* Restore AMR and UAMOR, set AMOR to all 1s */
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ld r5,VCPU_AMR(r4)
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ld r6,VCPU_UAMOR(r4)
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li r7,-1
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mtspr SPRN_AMR,r5
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mtspr SPRN_UAMOR,r6
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mtspr SPRN_AMOR,r7
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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/* Clear out SLB */
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li r6,0
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slbmte r6,r6
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slbia
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ptesync
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BEGIN_FTR_SECTION
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b 30f
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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/*
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* POWER7 host -> guest partition switch code.
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* We don't have to lock against concurrent tlbies,
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* but we do have to coordinate across hardware threads.
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*/
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/* Increment entry count iff exit count is zero. */
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ld r5,HSTATE_KVM_VCORE(r13)
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addi r9,r5,VCORE_ENTRY_EXIT
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21: lwarx r3,0,r9
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cmpwi r3,0x100 /* any threads starting to exit? */
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bge secondary_too_late /* if so we're too late to the party */
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addi r3,r3,1
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stwcx. r3,0,r9
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bne 21b
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/* Primary thread switches to guest partition. */
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ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
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lwz r6,VCPU_PTID(r4)
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cmpwi r6,0
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bne 20f
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ld r6,KVM_SDR1(r9)
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lwz r7,KVM_LPID(r9)
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li r0,LPID_RSVD /* switch to reserved LPID */
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mtspr SPRN_LPID,r0
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ptesync
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mtspr SPRN_SDR1,r6 /* switch to partition page table */
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mtspr SPRN_LPID,r7
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isync
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li r0,1
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stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
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b 10f
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/* Secondary threads wait for primary to have done partition switch */
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20: lbz r0,VCORE_IN_GUEST(r5)
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cmpwi r0,0
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beq 20b
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/* Set LPCR. Set the MER bit if there is a pending external irq. */
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10: ld r8,KVM_LPCR(r9)
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ld r0,VCPU_PENDING_EXC(r4)
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li r7,(1 << BOOK3S_IRQPRIO_EXTERNAL)
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oris r7,r7,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
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and. r0,r0,r7
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beq 11f
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ori r8,r8,LPCR_MER
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11: mtspr SPRN_LPCR,r8
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ld r8,KVM_RMOR(r9)
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mtspr SPRN_RMOR,r8
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isync
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/* Check if HDEC expires soon */
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mfspr r3,SPRN_HDEC
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cmpwi r3,10
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li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
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mr r9,r4
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blt hdec_soon
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/*
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* Invalidate the TLB if we could possibly have stale TLB
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* entries for this partition on this core due to the use
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* of tlbiel.
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* XXX maybe only need this on primary thread?
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*/
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ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
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lwz r5,VCPU_VCPUID(r4)
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lhz r6,PACAPACAINDEX(r13)
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rldimi r6,r5,0,62 /* XXX map as if threads 1:1 p:v */
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lhz r8,VCPU_LAST_CPU(r4)
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sldi r7,r6,1 /* see if this is the same vcpu */
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add r7,r7,r9 /* as last ran on this pcpu */
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lhz r0,KVM_LAST_VCPU(r7)
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cmpw r6,r8 /* on the same cpu core as last time? */
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bne 3f
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cmpw r0,r5 /* same vcpu as this core last ran? */
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beq 1f
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3: sth r6,VCPU_LAST_CPU(r4) /* if not, invalidate partition TLB */
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sth r5,KVM_LAST_VCPU(r7)
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li r6,128
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mtctr r6
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li r7,0x800 /* IS field = 0b10 */
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ptesync
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2: tlbiel r7
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addi r7,r7,0x1000
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bdnz 2b
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ptesync
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1:
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/* Save purr/spurr */
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mfspr r5,SPRN_PURR
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mfspr r6,SPRN_SPURR
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std r5,HSTATE_PURR(r13)
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std r6,HSTATE_SPURR(r13)
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ld r7,VCPU_PURR(r4)
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ld r8,VCPU_SPURR(r4)
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mtspr SPRN_PURR,r7
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mtspr SPRN_SPURR,r8
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b 31f
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/*
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* PPC970 host -> guest partition switch code.
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* We have to lock against concurrent tlbies,
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* using native_tlbie_lock to lock against host tlbies
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* and kvm->arch.tlbie_lock to lock against guest tlbies.
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* We also have to invalidate the TLB since its
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* entries aren't tagged with the LPID.
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*/
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30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
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/* first take native_tlbie_lock */
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.section ".toc","aw"
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toc_tlbie_lock:
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.tc native_tlbie_lock[TC],native_tlbie_lock
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.previous
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ld r3,toc_tlbie_lock@toc(2)
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lwz r8,PACA_LOCK_TOKEN(r13)
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24: lwarx r0,0,r3
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cmpwi r0,0
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bne 24b
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stwcx. r8,0,r3
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bne 24b
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isync
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ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */
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li r0,0x18f
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rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
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or r0,r7,r0
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ptesync
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sync
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mtspr SPRN_HID4,r0 /* switch to reserved LPID */
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isync
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li r0,0
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stw r0,0(r3) /* drop native_tlbie_lock */
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/* invalidate the whole TLB */
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li r0,256
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mtctr r0
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li r6,0
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25: tlbiel r6
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addi r6,r6,0x1000
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bdnz 25b
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ptesync
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/* Take the guest's tlbie_lock */
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addi r3,r9,KVM_TLBIE_LOCK
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24: lwarx r0,0,r3
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cmpwi r0,0
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bne 24b
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stwcx. r8,0,r3
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bne 24b
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isync
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ld r6,KVM_SDR1(r9)
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mtspr SPRN_SDR1,r6 /* switch to partition page table */
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/* Set up HID4 with the guest's LPID etc. */
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sync
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mtspr SPRN_HID4,r7
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isync
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/* drop the guest's tlbie_lock */
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li r0,0
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stw r0,0(r3)
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/* Check if HDEC expires soon */
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mfspr r3,SPRN_HDEC
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cmpwi r3,10
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li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
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mr r9,r4
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blt hdec_soon
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/* Enable HDEC interrupts */
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mfspr r0,SPRN_HID0
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li r3,1
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rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
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sync
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mtspr SPRN_HID0,r0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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/* Load up guest SLB entries */
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31: lwz r5,VCPU_SLB_MAX(r4)
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cmpwi r5,0
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beq 9f
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mtctr r5
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addi r6,r4,VCPU_SLB
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1: ld r8,VCPU_SLB_E(r6)
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ld r9,VCPU_SLB_V(r6)
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slbmte r9,r8
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addi r6,r6,VCPU_SLB_SIZE
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bdnz 1b
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9:
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/* Restore state of CTRL run bit; assume 1 on entry */
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lwz r5,VCPU_CTRL(r4)
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andi. r5,r5,1
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bne 4f
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mfspr r6,SPRN_CTRLF
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clrrdi r6,r6,1
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mtspr SPRN_CTRLT,r6
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4:
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ld r6, VCPU_CTR(r4)
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lwz r7, VCPU_XER(r4)
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mtctr r6
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mtxer r7
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/* Move SRR0 and SRR1 into the respective regs */
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ld r6, VCPU_SRR0(r4)
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ld r7, VCPU_SRR1(r4)
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mtspr SPRN_SRR0, r6
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mtspr SPRN_SRR1, r7
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ld r10, VCPU_PC(r4)
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ld r11, VCPU_MSR(r4) /* r10 = vcpu->arch.msr & ~MSR_HV */
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rldicl r11, r11, 63 - MSR_HV_LG, 1
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rotldi r11, r11, 1 + MSR_HV_LG
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ori r11, r11, MSR_ME
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fast_guest_return:
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mtspr SPRN_HSRR0,r10
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mtspr SPRN_HSRR1,r11
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/* Activate guest mode, so faults get handled by KVM */
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li r9, KVM_GUEST_MODE_GUEST
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stb r9, HSTATE_IN_GUEST(r13)
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|
|
|
/* Enter guest */
|
|
|
|
ld r5, VCPU_LR(r4)
|
|
lwz r6, VCPU_CR(r4)
|
|
mtlr r5
|
|
mtcr r6
|
|
|
|
ld r0, VCPU_GPR(r0)(r4)
|
|
ld r1, VCPU_GPR(r1)(r4)
|
|
ld r2, VCPU_GPR(r2)(r4)
|
|
ld r3, VCPU_GPR(r3)(r4)
|
|
ld r5, VCPU_GPR(r5)(r4)
|
|
ld r6, VCPU_GPR(r6)(r4)
|
|
ld r7, VCPU_GPR(r7)(r4)
|
|
ld r8, VCPU_GPR(r8)(r4)
|
|
ld r9, VCPU_GPR(r9)(r4)
|
|
ld r10, VCPU_GPR(r10)(r4)
|
|
ld r11, VCPU_GPR(r11)(r4)
|
|
ld r12, VCPU_GPR(r12)(r4)
|
|
ld r13, VCPU_GPR(r13)(r4)
|
|
|
|
ld r4, VCPU_GPR(r4)(r4)
|
|
|
|
hrfid
|
|
b .
|
|
|
|
/******************************************************************************
|
|
* *
|
|
* Exit code *
|
|
* *
|
|
*****************************************************************************/
|
|
|
|
/*
|
|
* We come here from the first-level interrupt handlers.
|
|
*/
|
|
.globl kvmppc_interrupt
|
|
kvmppc_interrupt:
|
|
/*
|
|
* Register contents:
|
|
* R12 = interrupt vector
|
|
* R13 = PACA
|
|
* guest CR, R12 saved in shadow VCPU SCRATCH1/0
|
|
* guest R13 saved in SPRN_SCRATCH0
|
|
*/
|
|
/* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
|
|
std r9, HSTATE_HOST_R2(r13)
|
|
ld r9, HSTATE_KVM_VCPU(r13)
|
|
|
|
/* Save registers */
|
|
|
|
std r0, VCPU_GPR(r0)(r9)
|
|
std r1, VCPU_GPR(r1)(r9)
|
|
std r2, VCPU_GPR(r2)(r9)
|
|
std r3, VCPU_GPR(r3)(r9)
|
|
std r4, VCPU_GPR(r4)(r9)
|
|
std r5, VCPU_GPR(r5)(r9)
|
|
std r6, VCPU_GPR(r6)(r9)
|
|
std r7, VCPU_GPR(r7)(r9)
|
|
std r8, VCPU_GPR(r8)(r9)
|
|
ld r0, HSTATE_HOST_R2(r13)
|
|
std r0, VCPU_GPR(r9)(r9)
|
|
std r10, VCPU_GPR(r10)(r9)
|
|
std r11, VCPU_GPR(r11)(r9)
|
|
ld r3, HSTATE_SCRATCH0(r13)
|
|
lwz r4, HSTATE_SCRATCH1(r13)
|
|
std r3, VCPU_GPR(r12)(r9)
|
|
stw r4, VCPU_CR(r9)
|
|
|
|
/* Restore R1/R2 so we can handle faults */
|
|
ld r1, HSTATE_HOST_R1(r13)
|
|
ld r2, PACATOC(r13)
|
|
|
|
mfspr r10, SPRN_SRR0
|
|
mfspr r11, SPRN_SRR1
|
|
std r10, VCPU_SRR0(r9)
|
|
std r11, VCPU_SRR1(r9)
|
|
andi. r0, r12, 2 /* need to read HSRR0/1? */
|
|
beq 1f
|
|
mfspr r10, SPRN_HSRR0
|
|
mfspr r11, SPRN_HSRR1
|
|
clrrdi r12, r12, 2
|
|
1: std r10, VCPU_PC(r9)
|
|
std r11, VCPU_MSR(r9)
|
|
|
|
GET_SCRATCH0(r3)
|
|
mflr r4
|
|
std r3, VCPU_GPR(r13)(r9)
|
|
std r4, VCPU_LR(r9)
|
|
|
|
/* Unset guest mode */
|
|
li r0, KVM_GUEST_MODE_NONE
|
|
stb r0, HSTATE_IN_GUEST(r13)
|
|
|
|
stw r12,VCPU_TRAP(r9)
|
|
|
|
/* See if this is a leftover HDEC interrupt */
|
|
cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
|
|
bne 2f
|
|
mfspr r3,SPRN_HDEC
|
|
cmpwi r3,0
|
|
bge ignore_hdec
|
|
2:
|
|
/* See if this is something we can handle in real mode */
|
|
cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
|
|
beq hcall_try_real_mode
|
|
hcall_real_cont:
|
|
|
|
/* Check for mediated interrupts (could be done earlier really ...) */
|
|
BEGIN_FTR_SECTION
|
|
cmpwi r12,BOOK3S_INTERRUPT_EXTERNAL
|
|
bne+ 1f
|
|
ld r5,VCPU_KVM(r9)
|
|
ld r5,KVM_LPCR(r5)
|
|
andi. r0,r11,MSR_EE
|
|
beq 1f
|
|
andi. r0,r5,LPCR_MER
|
|
bne bounce_ext_interrupt
|
|
1:
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
|
|
|
|
/* Save DEC */
|
|
mfspr r5,SPRN_DEC
|
|
mftb r6
|
|
extsw r5,r5
|
|
add r5,r5,r6
|
|
std r5,VCPU_DEC_EXPIRES(r9)
|
|
|
|
/* Save HEIR (HV emulation assist reg) in last_inst
|
|
if this is an HEI (HV emulation interrupt, e40) */
|
|
li r3,-1
|
|
BEGIN_FTR_SECTION
|
|
cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
|
|
bne 11f
|
|
mfspr r3,SPRN_HEIR
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
|
|
11: stw r3,VCPU_LAST_INST(r9)
|
|
|
|
/* Save more register state */
|
|
mfxer r5
|
|
mfdar r6
|
|
mfdsisr r7
|
|
mfctr r8
|
|
|
|
stw r5, VCPU_XER(r9)
|
|
std r6, VCPU_DAR(r9)
|
|
stw r7, VCPU_DSISR(r9)
|
|
std r8, VCPU_CTR(r9)
|
|
/* grab HDAR & HDSISR if HV data storage interrupt (HDSI) */
|
|
BEGIN_FTR_SECTION
|
|
cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
|
|
beq 6f
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
|
|
7: std r6, VCPU_FAULT_DAR(r9)
|
|
stw r7, VCPU_FAULT_DSISR(r9)
|
|
|
|
/* Save guest CTRL register, set runlatch to 1 */
|
|
mfspr r6,SPRN_CTRLF
|
|
stw r6,VCPU_CTRL(r9)
|
|
andi. r0,r6,1
|
|
bne 4f
|
|
ori r6,r6,1
|
|
mtspr SPRN_CTRLT,r6
|
|
4:
|
|
/* Read the guest SLB and save it away */
|
|
lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
|
|
mtctr r0
|
|
li r6,0
|
|
addi r7,r9,VCPU_SLB
|
|
li r5,0
|
|
1: slbmfee r8,r6
|
|
andis. r0,r8,SLB_ESID_V@h
|
|
beq 2f
|
|
add r8,r8,r6 /* put index in */
|
|
slbmfev r3,r6
|
|
std r8,VCPU_SLB_E(r7)
|
|
std r3,VCPU_SLB_V(r7)
|
|
addi r7,r7,VCPU_SLB_SIZE
|
|
addi r5,r5,1
|
|
2: addi r6,r6,1
|
|
bdnz 1b
|
|
stw r5,VCPU_SLB_MAX(r9)
|
|
|
|
/*
|
|
* Save the guest PURR/SPURR
|
|
*/
|
|
BEGIN_FTR_SECTION
|
|
mfspr r5,SPRN_PURR
|
|
mfspr r6,SPRN_SPURR
|
|
ld r7,VCPU_PURR(r9)
|
|
ld r8,VCPU_SPURR(r9)
|
|
std r5,VCPU_PURR(r9)
|
|
std r6,VCPU_SPURR(r9)
|
|
subf r5,r7,r5
|
|
subf r6,r8,r6
|
|
|
|
/*
|
|
* Restore host PURR/SPURR and add guest times
|
|
* so that the time in the guest gets accounted.
|
|
*/
|
|
ld r3,HSTATE_PURR(r13)
|
|
ld r4,HSTATE_SPURR(r13)
|
|
add r3,r3,r5
|
|
add r4,r4,r6
|
|
mtspr SPRN_PURR,r3
|
|
mtspr SPRN_SPURR,r4
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
|
|
|
|
/* Clear out SLB */
|
|
li r5,0
|
|
slbmte r5,r5
|
|
slbia
|
|
ptesync
|
|
|
|
hdec_soon:
|
|
BEGIN_FTR_SECTION
|
|
b 32f
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
|
|
/*
|
|
* POWER7 guest -> host partition switch code.
|
|
* We don't have to lock against tlbies but we do
|
|
* have to coordinate the hardware threads.
|
|
*/
|
|
/* Increment the threads-exiting-guest count in the 0xff00
|
|
bits of vcore->entry_exit_count */
|
|
lwsync
|
|
ld r5,HSTATE_KVM_VCORE(r13)
|
|
addi r6,r5,VCORE_ENTRY_EXIT
|
|
41: lwarx r3,0,r6
|
|
addi r0,r3,0x100
|
|
stwcx. r0,0,r6
|
|
bne 41b
|
|
|
|
/*
|
|
* At this point we have an interrupt that we have to pass
|
|
* up to the kernel or qemu; we can't handle it in real mode.
|
|
* Thus we have to do a partition switch, so we have to
|
|
* collect the other threads, if we are the first thread
|
|
* to take an interrupt. To do this, we set the HDEC to 0,
|
|
* which causes an HDEC interrupt in all threads within 2ns
|
|
* because the HDEC register is shared between all 4 threads.
|
|
* However, we don't need to bother if this is an HDEC
|
|
* interrupt, since the other threads will already be on their
|
|
* way here in that case.
|
|
*/
|
|
cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
|
|
beq 40f
|
|
cmpwi r3,0x100 /* Are we the first here? */
|
|
bge 40f
|
|
cmpwi r3,1
|
|
ble 40f
|
|
li r0,0
|
|
mtspr SPRN_HDEC,r0
|
|
40:
|
|
|
|
/* Secondary threads wait for primary to do partition switch */
|
|
ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
|
|
ld r5,HSTATE_KVM_VCORE(r13)
|
|
lwz r3,VCPU_PTID(r9)
|
|
cmpwi r3,0
|
|
beq 15f
|
|
HMT_LOW
|
|
13: lbz r3,VCORE_IN_GUEST(r5)
|
|
cmpwi r3,0
|
|
bne 13b
|
|
HMT_MEDIUM
|
|
b 16f
|
|
|
|
/* Primary thread waits for all the secondaries to exit guest */
|
|
15: lwz r3,VCORE_ENTRY_EXIT(r5)
|
|
srwi r0,r3,8
|
|
clrldi r3,r3,56
|
|
cmpw r3,r0
|
|
bne 15b
|
|
isync
|
|
|
|
/* Primary thread switches back to host partition */
|
|
ld r6,KVM_HOST_SDR1(r4)
|
|
lwz r7,KVM_HOST_LPID(r4)
|
|
li r8,LPID_RSVD /* switch to reserved LPID */
|
|
mtspr SPRN_LPID,r8
|
|
ptesync
|
|
mtspr SPRN_SDR1,r6 /* switch to partition page table */
|
|
mtspr SPRN_LPID,r7
|
|
isync
|
|
li r0,0
|
|
stb r0,VCORE_IN_GUEST(r5)
|
|
lis r8,0x7fff /* MAX_INT@h */
|
|
mtspr SPRN_HDEC,r8
|
|
|
|
16: ld r8,KVM_HOST_LPCR(r4)
|
|
mtspr SPRN_LPCR,r8
|
|
isync
|
|
b 33f
|
|
|
|
/*
|
|
* PPC970 guest -> host partition switch code.
|
|
* We have to lock against concurrent tlbies, and
|
|
* we have to flush the whole TLB.
|
|
*/
|
|
32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
|
|
|
|
/* Take the guest's tlbie_lock */
|
|
lwz r8,PACA_LOCK_TOKEN(r13)
|
|
addi r3,r4,KVM_TLBIE_LOCK
|
|
24: lwarx r0,0,r3
|
|
cmpwi r0,0
|
|
bne 24b
|
|
stwcx. r8,0,r3
|
|
bne 24b
|
|
isync
|
|
|
|
ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
|
|
li r0,0x18f
|
|
rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
|
|
or r0,r7,r0
|
|
ptesync
|
|
sync
|
|
mtspr SPRN_HID4,r0 /* switch to reserved LPID */
|
|
isync
|
|
li r0,0
|
|
stw r0,0(r3) /* drop guest tlbie_lock */
|
|
|
|
/* invalidate the whole TLB */
|
|
li r0,256
|
|
mtctr r0
|
|
li r6,0
|
|
25: tlbiel r6
|
|
addi r6,r6,0x1000
|
|
bdnz 25b
|
|
ptesync
|
|
|
|
/* take native_tlbie_lock */
|
|
ld r3,toc_tlbie_lock@toc(2)
|
|
24: lwarx r0,0,r3
|
|
cmpwi r0,0
|
|
bne 24b
|
|
stwcx. r8,0,r3
|
|
bne 24b
|
|
isync
|
|
|
|
ld r6,KVM_HOST_SDR1(r4)
|
|
mtspr SPRN_SDR1,r6 /* switch to host page table */
|
|
|
|
/* Set up host HID4 value */
|
|
sync
|
|
mtspr SPRN_HID4,r7
|
|
isync
|
|
li r0,0
|
|
stw r0,0(r3) /* drop native_tlbie_lock */
|
|
|
|
lis r8,0x7fff /* MAX_INT@h */
|
|
mtspr SPRN_HDEC,r8
|
|
|
|
/* Disable HDEC interrupts */
|
|
mfspr r0,SPRN_HID0
|
|
li r3,0
|
|
rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
|
|
sync
|
|
mtspr SPRN_HID0,r0
|
|
mfspr r0,SPRN_HID0
|
|
mfspr r0,SPRN_HID0
|
|
mfspr r0,SPRN_HID0
|
|
mfspr r0,SPRN_HID0
|
|
mfspr r0,SPRN_HID0
|
|
mfspr r0,SPRN_HID0
|
|
|
|
/* load host SLB entries */
|
|
33: ld r8,PACA_SLBSHADOWPTR(r13)
|
|
|
|
.rept SLB_NUM_BOLTED
|
|
ld r5,SLBSHADOW_SAVEAREA(r8)
|
|
ld r6,SLBSHADOW_SAVEAREA+8(r8)
|
|
andis. r7,r5,SLB_ESID_V@h
|
|
beq 1f
|
|
slbmte r6,r5
|
|
1: addi r8,r8,16
|
|
.endr
|
|
|
|
/* Save and reset AMR and UAMOR before turning on the MMU */
|
|
BEGIN_FTR_SECTION
|
|
mfspr r5,SPRN_AMR
|
|
mfspr r6,SPRN_UAMOR
|
|
std r5,VCPU_AMR(r9)
|
|
std r6,VCPU_UAMOR(r9)
|
|
li r6,0
|
|
mtspr SPRN_AMR,r6
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
|
|
|
|
/* Restore host DABR and DABRX */
|
|
ld r5,HSTATE_DABR(r13)
|
|
li r6,7
|
|
mtspr SPRN_DABR,r5
|
|
mtspr SPRN_DABRX,r6
|
|
|
|
/* Switch DSCR back to host value */
|
|
BEGIN_FTR_SECTION
|
|
mfspr r8, SPRN_DSCR
|
|
ld r7, HSTATE_DSCR(r13)
|
|
std r8, VCPU_DSCR(r7)
|
|
mtspr SPRN_DSCR, r7
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
|
|
|
|
/* Save non-volatile GPRs */
|
|
std r14, VCPU_GPR(r14)(r9)
|
|
std r15, VCPU_GPR(r15)(r9)
|
|
std r16, VCPU_GPR(r16)(r9)
|
|
std r17, VCPU_GPR(r17)(r9)
|
|
std r18, VCPU_GPR(r18)(r9)
|
|
std r19, VCPU_GPR(r19)(r9)
|
|
std r20, VCPU_GPR(r20)(r9)
|
|
std r21, VCPU_GPR(r21)(r9)
|
|
std r22, VCPU_GPR(r22)(r9)
|
|
std r23, VCPU_GPR(r23)(r9)
|
|
std r24, VCPU_GPR(r24)(r9)
|
|
std r25, VCPU_GPR(r25)(r9)
|
|
std r26, VCPU_GPR(r26)(r9)
|
|
std r27, VCPU_GPR(r27)(r9)
|
|
std r28, VCPU_GPR(r28)(r9)
|
|
std r29, VCPU_GPR(r29)(r9)
|
|
std r30, VCPU_GPR(r30)(r9)
|
|
std r31, VCPU_GPR(r31)(r9)
|
|
|
|
/* Save SPRGs */
|
|
mfspr r3, SPRN_SPRG0
|
|
mfspr r4, SPRN_SPRG1
|
|
mfspr r5, SPRN_SPRG2
|
|
mfspr r6, SPRN_SPRG3
|
|
std r3, VCPU_SPRG0(r9)
|
|
std r4, VCPU_SPRG1(r9)
|
|
std r5, VCPU_SPRG2(r9)
|
|
std r6, VCPU_SPRG3(r9)
|
|
|
|
/* Increment yield count if they have a VPA */
|
|
ld r8, VCPU_VPA(r9) /* do they have a VPA? */
|
|
cmpdi r8, 0
|
|
beq 25f
|
|
lwz r3, LPPACA_YIELDCOUNT(r8)
|
|
addi r3, r3, 1
|
|
stw r3, LPPACA_YIELDCOUNT(r8)
|
|
25:
|
|
/* Save PMU registers if requested */
|
|
/* r8 and cr0.eq are live here */
|
|
li r3, 1
|
|
sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
|
|
mfspr r4, SPRN_MMCR0 /* save MMCR0 */
|
|
mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
|
|
isync
|
|
beq 21f /* if no VPA, save PMU stuff anyway */
|
|
lbz r7, LPPACA_PMCINUSE(r8)
|
|
cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
|
|
bne 21f
|
|
std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
|
|
b 22f
|
|
21: mfspr r5, SPRN_MMCR1
|
|
mfspr r6, SPRN_MMCRA
|
|
std r4, VCPU_MMCR(r9)
|
|
std r5, VCPU_MMCR + 8(r9)
|
|
std r6, VCPU_MMCR + 16(r9)
|
|
mfspr r3, SPRN_PMC1
|
|
mfspr r4, SPRN_PMC2
|
|
mfspr r5, SPRN_PMC3
|
|
mfspr r6, SPRN_PMC4
|
|
mfspr r7, SPRN_PMC5
|
|
mfspr r8, SPRN_PMC6
|
|
BEGIN_FTR_SECTION
|
|
mfspr r10, SPRN_PMC7
|
|
mfspr r11, SPRN_PMC8
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
|
|
stw r3, VCPU_PMC(r9)
|
|
stw r4, VCPU_PMC + 4(r9)
|
|
stw r5, VCPU_PMC + 8(r9)
|
|
stw r6, VCPU_PMC + 12(r9)
|
|
stw r7, VCPU_PMC + 16(r9)
|
|
stw r8, VCPU_PMC + 20(r9)
|
|
BEGIN_FTR_SECTION
|
|
stw r10, VCPU_PMC + 24(r9)
|
|
stw r11, VCPU_PMC + 28(r9)
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
|
|
22:
|
|
/* save FP state */
|
|
mr r3, r9
|
|
bl .kvmppc_save_fp
|
|
|
|
/* Secondary threads go off to take a nap on POWER7 */
|
|
BEGIN_FTR_SECTION
|
|
lwz r0,VCPU_PTID(r3)
|
|
cmpwi r0,0
|
|
bne secondary_nap
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
|
|
|
|
/*
|
|
* Reload DEC. HDEC interrupts were disabled when
|
|
* we reloaded the host's LPCR value.
|
|
*/
|
|
ld r3, HSTATE_DECEXP(r13)
|
|
mftb r4
|
|
subf r4, r4, r3
|
|
mtspr SPRN_DEC, r4
|
|
|
|
/* Reload the host's PMU registers */
|
|
ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
|
|
lbz r4, LPPACA_PMCINUSE(r3)
|
|
cmpwi r4, 0
|
|
beq 23f /* skip if not */
|
|
lwz r3, HSTATE_PMC(r13)
|
|
lwz r4, HSTATE_PMC + 4(r13)
|
|
lwz r5, HSTATE_PMC + 8(r13)
|
|
lwz r6, HSTATE_PMC + 12(r13)
|
|
lwz r8, HSTATE_PMC + 16(r13)
|
|
lwz r9, HSTATE_PMC + 20(r13)
|
|
BEGIN_FTR_SECTION
|
|
lwz r10, HSTATE_PMC + 24(r13)
|
|
lwz r11, HSTATE_PMC + 28(r13)
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
|
|
mtspr SPRN_PMC1, r3
|
|
mtspr SPRN_PMC2, r4
|
|
mtspr SPRN_PMC3, r5
|
|
mtspr SPRN_PMC4, r6
|
|
mtspr SPRN_PMC5, r8
|
|
mtspr SPRN_PMC6, r9
|
|
BEGIN_FTR_SECTION
|
|
mtspr SPRN_PMC7, r10
|
|
mtspr SPRN_PMC8, r11
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
|
|
ld r3, HSTATE_MMCR(r13)
|
|
ld r4, HSTATE_MMCR + 8(r13)
|
|
ld r5, HSTATE_MMCR + 16(r13)
|
|
mtspr SPRN_MMCR1, r4
|
|
mtspr SPRN_MMCRA, r5
|
|
mtspr SPRN_MMCR0, r3
|
|
isync
|
|
23:
|
|
/*
|
|
* For external and machine check interrupts, we need
|
|
* to call the Linux handler to process the interrupt.
|
|
* We do that by jumping to the interrupt vector address
|
|
* which we have in r12. The [h]rfid at the end of the
|
|
* handler will return to the book3s_hv_interrupts.S code.
|
|
* For other interrupts we do the rfid to get back
|
|
* to the book3s_interrupts.S code here.
|
|
*/
|
|
ld r8, HSTATE_VMHANDLER(r13)
|
|
ld r7, HSTATE_HOST_MSR(r13)
|
|
|
|
cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
|
|
beq 11f
|
|
cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
|
|
|
|
/* RFI into the highmem handler, or branch to interrupt handler */
|
|
12: mfmsr r6
|
|
mtctr r12
|
|
li r0, MSR_RI
|
|
andc r6, r6, r0
|
|
mtmsrd r6, 1 /* Clear RI in MSR */
|
|
mtsrr0 r8
|
|
mtsrr1 r7
|
|
beqctr
|
|
RFI
|
|
|
|
11:
|
|
BEGIN_FTR_SECTION
|
|
b 12b
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
|
|
mtspr SPRN_HSRR0, r8
|
|
mtspr SPRN_HSRR1, r7
|
|
ba 0x500
|
|
|
|
6: mfspr r6,SPRN_HDAR
|
|
mfspr r7,SPRN_HDSISR
|
|
b 7b
|
|
|
|
/*
|
|
* Try to handle an hcall in real mode.
|
|
* Returns to the guest if we handle it, or continues on up to
|
|
* the kernel if we can't (i.e. if we don't have a handler for
|
|
* it, or if the handler returns H_TOO_HARD).
|
|
*/
|
|
.globl hcall_try_real_mode
|
|
hcall_try_real_mode:
|
|
ld r3,VCPU_GPR(r3)(r9)
|
|
andi. r0,r11,MSR_PR
|
|
bne hcall_real_cont
|
|
clrrdi r3,r3,2
|
|
cmpldi r3,hcall_real_table_end - hcall_real_table
|
|
bge hcall_real_cont
|
|
LOAD_REG_ADDR(r4, hcall_real_table)
|
|
lwzx r3,r3,r4
|
|
cmpwi r3,0
|
|
beq hcall_real_cont
|
|
add r3,r3,r4
|
|
mtctr r3
|
|
mr r3,r9 /* get vcpu pointer */
|
|
ld r4,VCPU_GPR(r4)(r9)
|
|
bctrl
|
|
cmpdi r3,H_TOO_HARD
|
|
beq hcall_real_fallback
|
|
ld r4,HSTATE_KVM_VCPU(r13)
|
|
std r3,VCPU_GPR(r3)(r4)
|
|
ld r10,VCPU_PC(r4)
|
|
ld r11,VCPU_MSR(r4)
|
|
b fast_guest_return
|
|
|
|
/* We've attempted a real mode hcall, but it's punted it back
|
|
* to userspace. We need to restore some clobbered volatiles
|
|
* before resuming the pass-it-to-qemu path */
|
|
hcall_real_fallback:
|
|
li r12,BOOK3S_INTERRUPT_SYSCALL
|
|
ld r9, HSTATE_KVM_VCPU(r13)
|
|
ld r11, VCPU_MSR(r9)
|
|
|
|
b hcall_real_cont
|
|
|
|
.globl hcall_real_table
|
|
hcall_real_table:
|
|
.long 0 /* 0 - unused */
|
|
.long .kvmppc_h_remove - hcall_real_table
|
|
.long .kvmppc_h_enter - hcall_real_table
|
|
.long .kvmppc_h_read - hcall_real_table
|
|
.long 0 /* 0x10 - H_CLEAR_MOD */
|
|
.long 0 /* 0x14 - H_CLEAR_REF */
|
|
.long .kvmppc_h_protect - hcall_real_table
|
|
.long 0 /* 0x1c - H_GET_TCE */
|
|
.long .kvmppc_h_put_tce - hcall_real_table
|
|
.long 0 /* 0x24 - H_SET_SPRG0 */
|
|
.long .kvmppc_h_set_dabr - hcall_real_table
|
|
.long 0 /* 0x2c */
|
|
.long 0 /* 0x30 */
|
|
.long 0 /* 0x34 */
|
|
.long 0 /* 0x38 */
|
|
.long 0 /* 0x3c */
|
|
.long 0 /* 0x40 */
|
|
.long 0 /* 0x44 */
|
|
.long 0 /* 0x48 */
|
|
.long 0 /* 0x4c */
|
|
.long 0 /* 0x50 */
|
|
.long 0 /* 0x54 */
|
|
.long 0 /* 0x58 */
|
|
.long 0 /* 0x5c */
|
|
.long 0 /* 0x60 */
|
|
.long 0 /* 0x64 */
|
|
.long 0 /* 0x68 */
|
|
.long 0 /* 0x6c */
|
|
.long 0 /* 0x70 */
|
|
.long 0 /* 0x74 */
|
|
.long 0 /* 0x78 */
|
|
.long 0 /* 0x7c */
|
|
.long 0 /* 0x80 */
|
|
.long 0 /* 0x84 */
|
|
.long 0 /* 0x88 */
|
|
.long 0 /* 0x8c */
|
|
.long 0 /* 0x90 */
|
|
.long 0 /* 0x94 */
|
|
.long 0 /* 0x98 */
|
|
.long 0 /* 0x9c */
|
|
.long 0 /* 0xa0 */
|
|
.long 0 /* 0xa4 */
|
|
.long 0 /* 0xa8 */
|
|
.long 0 /* 0xac */
|
|
.long 0 /* 0xb0 */
|
|
.long 0 /* 0xb4 */
|
|
.long 0 /* 0xb8 */
|
|
.long 0 /* 0xbc */
|
|
.long 0 /* 0xc0 */
|
|
.long 0 /* 0xc4 */
|
|
.long 0 /* 0xc8 */
|
|
.long 0 /* 0xcc */
|
|
.long 0 /* 0xd0 */
|
|
.long 0 /* 0xd4 */
|
|
.long 0 /* 0xd8 */
|
|
.long 0 /* 0xdc */
|
|
.long 0 /* 0xe0 */
|
|
.long 0 /* 0xe4 */
|
|
.long 0 /* 0xe8 */
|
|
.long 0 /* 0xec */
|
|
.long 0 /* 0xf0 */
|
|
.long 0 /* 0xf4 */
|
|
.long 0 /* 0xf8 */
|
|
.long 0 /* 0xfc */
|
|
.long 0 /* 0x100 */
|
|
.long 0 /* 0x104 */
|
|
.long 0 /* 0x108 */
|
|
.long 0 /* 0x10c */
|
|
.long 0 /* 0x110 */
|
|
.long 0 /* 0x114 */
|
|
.long 0 /* 0x118 */
|
|
.long 0 /* 0x11c */
|
|
.long 0 /* 0x120 */
|
|
.long .kvmppc_h_bulk_remove - hcall_real_table
|
|
hcall_real_table_end:
|
|
|
|
ignore_hdec:
|
|
mr r4,r9
|
|
b fast_guest_return
|
|
|
|
bounce_ext_interrupt:
|
|
mr r4,r9
|
|
mtspr SPRN_SRR0,r10
|
|
mtspr SPRN_SRR1,r11
|
|
li r10,BOOK3S_INTERRUPT_EXTERNAL
|
|
LOAD_REG_IMMEDIATE(r11,MSR_SF | MSR_ME);
|
|
b fast_guest_return
|
|
|
|
_GLOBAL(kvmppc_h_set_dabr)
|
|
std r4,VCPU_DABR(r3)
|
|
mtspr SPRN_DABR,r4
|
|
li r3,0
|
|
blr
|
|
|
|
secondary_too_late:
|
|
ld r5,HSTATE_KVM_VCORE(r13)
|
|
HMT_LOW
|
|
13: lbz r3,VCORE_IN_GUEST(r5)
|
|
cmpwi r3,0
|
|
bne 13b
|
|
HMT_MEDIUM
|
|
ld r11,PACA_SLBSHADOWPTR(r13)
|
|
|
|
.rept SLB_NUM_BOLTED
|
|
ld r5,SLBSHADOW_SAVEAREA(r11)
|
|
ld r6,SLBSHADOW_SAVEAREA+8(r11)
|
|
andis. r7,r5,SLB_ESID_V@h
|
|
beq 1f
|
|
slbmte r6,r5
|
|
1: addi r11,r11,16
|
|
.endr
|
|
b 50f
|
|
|
|
secondary_nap:
|
|
/* Clear any pending IPI */
|
|
50: ld r5, HSTATE_XICS_PHYS(r13)
|
|
li r0, 0xff
|
|
li r6, XICS_QIRR
|
|
stbcix r0, r5, r6
|
|
|
|
/* increment the nap count and then go to nap mode */
|
|
ld r4, HSTATE_KVM_VCORE(r13)
|
|
addi r4, r4, VCORE_NAP_COUNT
|
|
lwsync /* make previous updates visible */
|
|
51: lwarx r3, 0, r4
|
|
addi r3, r3, 1
|
|
stwcx. r3, 0, r4
|
|
bne 51b
|
|
isync
|
|
|
|
mfspr r4, SPRN_LPCR
|
|
li r0, LPCR_PECE
|
|
andc r4, r4, r0
|
|
ori r4, r4, LPCR_PECE0 /* exit nap on interrupt */
|
|
mtspr SPRN_LPCR, r4
|
|
li r0, 0
|
|
std r0, HSTATE_SCRATCH0(r13)
|
|
ptesync
|
|
ld r0, HSTATE_SCRATCH0(r13)
|
|
1: cmpd r0, r0
|
|
bne 1b
|
|
nap
|
|
b .
|
|
|
|
/*
|
|
* Save away FP, VMX and VSX registers.
|
|
* r3 = vcpu pointer
|
|
*/
|
|
_GLOBAL(kvmppc_save_fp)
|
|
mfmsr r9
|
|
ori r8,r9,MSR_FP
|
|
#ifdef CONFIG_ALTIVEC
|
|
BEGIN_FTR_SECTION
|
|
oris r8,r8,MSR_VEC@h
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
#endif
|
|
#ifdef CONFIG_VSX
|
|
BEGIN_FTR_SECTION
|
|
oris r8,r8,MSR_VSX@h
|
|
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
|
|
#endif
|
|
mtmsrd r8
|
|
isync
|
|
#ifdef CONFIG_VSX
|
|
BEGIN_FTR_SECTION
|
|
reg = 0
|
|
.rept 32
|
|
li r6,reg*16+VCPU_VSRS
|
|
stxvd2x reg,r6,r3
|
|
reg = reg + 1
|
|
.endr
|
|
FTR_SECTION_ELSE
|
|
#endif
|
|
reg = 0
|
|
.rept 32
|
|
stfd reg,reg*8+VCPU_FPRS(r3)
|
|
reg = reg + 1
|
|
.endr
|
|
#ifdef CONFIG_VSX
|
|
ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
|
|
#endif
|
|
mffs fr0
|
|
stfd fr0,VCPU_FPSCR(r3)
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
BEGIN_FTR_SECTION
|
|
reg = 0
|
|
.rept 32
|
|
li r6,reg*16+VCPU_VRS
|
|
stvx reg,r6,r3
|
|
reg = reg + 1
|
|
.endr
|
|
mfvscr vr0
|
|
li r6,VCPU_VSCR
|
|
stvx vr0,r6,r3
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
#endif
|
|
mfspr r6,SPRN_VRSAVE
|
|
stw r6,VCPU_VRSAVE(r3)
|
|
mtmsrd r9
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Load up FP, VMX and VSX registers
|
|
* r4 = vcpu pointer
|
|
*/
|
|
.globl kvmppc_load_fp
|
|
kvmppc_load_fp:
|
|
mfmsr r9
|
|
ori r8,r9,MSR_FP
|
|
#ifdef CONFIG_ALTIVEC
|
|
BEGIN_FTR_SECTION
|
|
oris r8,r8,MSR_VEC@h
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
#endif
|
|
#ifdef CONFIG_VSX
|
|
BEGIN_FTR_SECTION
|
|
oris r8,r8,MSR_VSX@h
|
|
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
|
|
#endif
|
|
mtmsrd r8
|
|
isync
|
|
lfd fr0,VCPU_FPSCR(r4)
|
|
MTFSF_L(fr0)
|
|
#ifdef CONFIG_VSX
|
|
BEGIN_FTR_SECTION
|
|
reg = 0
|
|
.rept 32
|
|
li r7,reg*16+VCPU_VSRS
|
|
lxvd2x reg,r7,r4
|
|
reg = reg + 1
|
|
.endr
|
|
FTR_SECTION_ELSE
|
|
#endif
|
|
reg = 0
|
|
.rept 32
|
|
lfd reg,reg*8+VCPU_FPRS(r4)
|
|
reg = reg + 1
|
|
.endr
|
|
#ifdef CONFIG_VSX
|
|
ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
|
|
#endif
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
BEGIN_FTR_SECTION
|
|
li r7,VCPU_VSCR
|
|
lvx vr0,r7,r4
|
|
mtvscr vr0
|
|
reg = 0
|
|
.rept 32
|
|
li r7,reg*16+VCPU_VRS
|
|
lvx reg,r7,r4
|
|
reg = reg + 1
|
|
.endr
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
#endif
|
|
lwz r7,VCPU_VRSAVE(r4)
|
|
mtspr SPRN_VRSAVE,r7
|
|
blr
|