747 lines
21 KiB
Plaintext
747 lines
21 KiB
Plaintext
/*
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* Device Tree Source for the r8a7796 SoC
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*
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* Copyright (C) 2016 Renesas Electronics Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7796-sysc.h>
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/ {
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compatible = "renesas,r8a7796";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 1 core only at this point */
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a57_0: cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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};
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L2_CA57: cache-controller@0 {
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compatible = "cache";
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reg = <0>;
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power-domains = <&sysc R8A7796_PD_CA57_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x20000>,
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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wdt0: watchdog@e6020000 {
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compatible = "renesas,r8a7796-wdt",
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"renesas,rcar-gen3-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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clocks = <&cpg CPG_MOD 402>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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status = "disabled";
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7796",
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"renesas,gpio-rcar";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 16>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7796",
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"renesas,gpio-rcar";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 29>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7796",
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"renesas,gpio-rcar";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 15>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7796",
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"renesas,gpio-rcar";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 16>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7796",
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"renesas,gpio-rcar";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 18>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7796",
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"renesas,gpio-rcar";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7796",
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"renesas,gpio-rcar";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 906>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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gpio7: gpio@e6055800 {
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compatible = "renesas,gpio-r8a7796",
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"renesas,gpio-rcar";
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reg = <0 0xe6055800 0 0x50>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 4>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 905>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7796";
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reg = <0 0xe6060000 0 0x50c>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7796-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7796-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7796-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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i2c0: i2c@e6500000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7796",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe6500000 0 0x40>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 931>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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dmas = <&dmac1 0x91>, <&dmac1 0x90>,
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<&dmac2 0x91>, <&dmac2 0x90>;
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dma-names = "tx", "rx", "tx", "rx";
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i2c-scl-internal-delay-ns = <110>;
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status = "disabled";
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};
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i2c1: i2c@e6508000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7796",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe6508000 0 0x40>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 930>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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dmas = <&dmac1 0x93>, <&dmac1 0x92>,
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<&dmac2 0x93>, <&dmac2 0x92>;
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dma-names = "tx", "rx", "tx", "rx";
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c2: i2c@e6510000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7796",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe6510000 0 0x40>;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 929>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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dmas = <&dmac1 0x95>, <&dmac1 0x94>,
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<&dmac2 0x95>, <&dmac2 0x94>;
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dma-names = "tx", "rx", "tx", "rx";
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c3: i2c@e66d0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7796",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe66d0000 0 0x40>;
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interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 928>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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dmas = <&dmac0 0x97>, <&dmac0 0x96>;
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dma-names = "tx", "rx";
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i2c-scl-internal-delay-ns = <110>;
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status = "disabled";
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};
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i2c4: i2c@e66d8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7796",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe66d8000 0 0x40>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 927>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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dmas = <&dmac0 0x99>, <&dmac0 0x98>;
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dma-names = "tx", "rx";
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i2c-scl-internal-delay-ns = <110>;
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status = "disabled";
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};
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i2c5: i2c@e66e0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7796",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe66e0000 0 0x40>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 919>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
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dma-names = "tx", "rx";
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i2c-scl-internal-delay-ns = <110>;
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status = "disabled";
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};
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i2c6: i2c@e66e8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7796",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe66e8000 0 0x40>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 918>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
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dma-names = "tx", "rx";
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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can0: can@e6c30000 {
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compatible = "renesas,can-r8a7796",
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"renesas,rcar-gen3-can";
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reg = <0 0xe6c30000 0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 916>,
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<&cpg CPG_CORE R8A7796_CLK_CANFD>,
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<&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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status = "disabled";
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};
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can1: can@e6c38000 {
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compatible = "renesas,can-r8a7796",
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"renesas,rcar-gen3-can";
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reg = <0 0xe6c38000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 915>,
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<&cpg CPG_CORE R8A7796_CLK_CANFD>,
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<&can_clk>;
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clock-names = "clkp1", "clkp2", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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status = "disabled";
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};
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canfd: can@e66c0000 {
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compatible = "renesas,r8a7796-canfd",
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"renesas,rcar-gen3-canfd";
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reg = <0 0xe66c0000 0 0x8000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 914>,
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<&cpg CPG_CORE R8A7796_CLK_CANFD>,
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<&can_clk>;
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clock-names = "fck", "canfd", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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status = "disabled";
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channel0 {
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status = "disabled";
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};
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channel1 {
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status = "disabled";
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};
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a7796",
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"renesas,etheravb-rcar-gen3";
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reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 812>;
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
phy-mode = "rgmii-id";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e88000 {
|
|
compatible = "renesas,scif-r8a7796",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e88000 0 64>;
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 310>,
|
|
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e90000 {
|
|
compatible = "renesas,msiof-r8a7796",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6e90000 0 0x0064>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 211>;
|
|
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
|
<&dmac2 0x41>, <&dmac2 0x40>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6ea0000 {
|
|
compatible = "renesas,msiof-r8a7796",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6ea0000 0 0x0064>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 210>;
|
|
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
|
<&dmac2 0x43>, <&dmac2 0x42>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6c00000 {
|
|
compatible = "renesas,msiof-r8a7796",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c00000 0 0x0064>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 209>;
|
|
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof3: spi@e6c10000 {
|
|
compatible = "renesas,msiof-r8a7796",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c10000 0 0x0064>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 208>;
|
|
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmac0: dma-controller@e6700000 {
|
|
compatible = "renesas,dmac-r8a7796",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe6700000 0 0x10000>;
|
|
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 219>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
};
|
|
|
|
dmac1: dma-controller@e7300000 {
|
|
compatible = "renesas,dmac-r8a7796",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe7300000 0 0x10000>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 218>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
};
|
|
|
|
dmac2: dma-controller@e7310000 {
|
|
compatible = "renesas,dmac-r8a7796",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe7310000 0 0x10000>;
|
|
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 217>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
};
|
|
|
|
sdhi0: sd@ee100000 {
|
|
compatible = "renesas,sdhi-r8a7796";
|
|
reg = <0 0xee100000 0 0x2000>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 314>;
|
|
max-frequency = <200000000>;
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi1: sd@ee120000 {
|
|
compatible = "renesas,sdhi-r8a7796";
|
|
reg = <0 0xee120000 0 0x2000>;
|
|
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 313>;
|
|
max-frequency = <200000000>;
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi2: sd@ee140000 {
|
|
compatible = "renesas,sdhi-r8a7796";
|
|
reg = <0 0xee140000 0 0x2000>;
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 312>;
|
|
max-frequency = <200000000>;
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi3: sd@ee160000 {
|
|
compatible = "renesas,sdhi-r8a7796";
|
|
reg = <0 0xee160000 0 0x2000>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 311>;
|
|
max-frequency = <200000000>;
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tsc: thermal@e6198000 {
|
|
compatible = "renesas,r8a7796-thermal";
|
|
reg = <0 0xe6198000 0 0x68>,
|
|
<0 0xe61a0000 0 0x5c>,
|
|
<0 0xe61a8000 0 0x5c>;
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 522>;
|
|
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
|
#thermal-sensor-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
thermal-zones {
|
|
sensor_thermal1: sensor-thermal1 {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 0>;
|
|
|
|
trips {
|
|
sensor1_crit: sensor1-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
sensor_thermal2: sensor-thermal2 {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 1>;
|
|
|
|
trips {
|
|
sensor2_crit: sensor2-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
sensor_thermal3: sensor-thermal3 {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsc 2>;
|
|
|
|
trips {
|
|
sensor3_crit: sensor3-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|