161 lines
3.1 KiB
Plaintext
161 lines
3.1 KiB
Plaintext
/*
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* dts file for Hisilicon Hi3660 SoC
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*
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* Copyright (C) 2016, Hisilicon Ltd.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "hisilicon,hi3660";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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cpu4: cpu@100 {
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compatible = "arm,cortex-a73", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu5: cpu@101 {
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compatible = "arm,cortex-a73", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x101>;
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enable-method = "psci";
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};
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cpu6: cpu@102 {
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compatible = "arm,cortex-a73", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x102>;
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enable-method = "psci";
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};
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cpu7: cpu@103 {
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compatible = "arm,cortex-a73", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x103>;
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enable-method = "psci";
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};
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};
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gic: interrupt-controller@e82b0000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
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<0x0 0xe82b2000 0 0x2000>, /* GICC */
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<0x0 0xe82b4000 0 0x2000>, /* GICH */
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<0x0 0xe82b6000 0 0x2000>; /* GICV */
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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fixed_uart5: fixed_19_2M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "fixed:uart5";
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};
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uart5: uart@fdf05000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfdf05000 0x0 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fixed_uart5 &fixed_uart5>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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