451 lines
12 KiB
C
451 lines
12 KiB
C
/*
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* Copyright (C) 2015 Free Electrons
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* Copyright (C) 2015 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <linux/component.h>
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#include <linux/reset.h>
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#include "sun4i_backend.h"
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#include "sun4i_drv.h"
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static const u32 sunxi_rgb2yuv_coef[12] = {
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0x00000107, 0x00000204, 0x00000064, 0x00000108,
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0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
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0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
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};
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void sun4i_backend_apply_color_correction(struct sun4i_backend *backend)
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{
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int i;
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DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
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/* Set color correction */
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regmap_write(backend->regs, SUN4I_BACKEND_OCCTL_REG,
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SUN4I_BACKEND_OCCTL_ENABLE);
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for (i = 0; i < 12; i++)
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regmap_write(backend->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
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sunxi_rgb2yuv_coef[i]);
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}
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EXPORT_SYMBOL(sun4i_backend_apply_color_correction);
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void sun4i_backend_disable_color_correction(struct sun4i_backend *backend)
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{
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DRM_DEBUG_DRIVER("Disabling color correction\n");
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/* Disable color correction */
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regmap_update_bits(backend->regs, SUN4I_BACKEND_OCCTL_REG,
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SUN4I_BACKEND_OCCTL_ENABLE, 0);
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}
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EXPORT_SYMBOL(sun4i_backend_disable_color_correction);
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void sun4i_backend_commit(struct sun4i_backend *backend)
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{
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DRM_DEBUG_DRIVER("Committing changes\n");
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regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
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SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
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SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
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}
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EXPORT_SYMBOL(sun4i_backend_commit);
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void sun4i_backend_layer_enable(struct sun4i_backend *backend,
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int layer, bool enable)
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{
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u32 val;
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DRM_DEBUG_DRIVER("Enabling layer %d\n", layer);
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if (enable)
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val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
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else
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val = 0;
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regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
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SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
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}
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EXPORT_SYMBOL(sun4i_backend_layer_enable);
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static int sun4i_backend_drm_format_to_layer(struct drm_plane *plane,
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u32 format, u32 *mode)
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{
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if ((plane->type == DRM_PLANE_TYPE_PRIMARY) &&
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(format == DRM_FORMAT_ARGB8888))
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format = DRM_FORMAT_XRGB8888;
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switch (format) {
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case DRM_FORMAT_ARGB8888:
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*mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
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break;
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case DRM_FORMAT_ARGB4444:
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*mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
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break;
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case DRM_FORMAT_ARGB1555:
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*mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
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break;
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case DRM_FORMAT_RGBA5551:
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*mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
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break;
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case DRM_FORMAT_RGBA4444:
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*mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
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break;
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case DRM_FORMAT_XRGB8888:
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*mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
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break;
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case DRM_FORMAT_RGB888:
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*mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
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break;
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case DRM_FORMAT_RGB565:
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*mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
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int layer, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
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if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
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DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
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state->crtc_w, state->crtc_h);
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regmap_write(backend->regs, SUN4I_BACKEND_DISSIZE_REG,
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SUN4I_BACKEND_DISSIZE(state->crtc_w,
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state->crtc_h));
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}
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/* Set the line width */
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DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
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regmap_write(backend->regs, SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
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fb->pitches[0] * 8);
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/* Set height and width */
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DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
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state->crtc_w, state->crtc_h);
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regmap_write(backend->regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
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SUN4I_BACKEND_LAYSIZE(state->crtc_w,
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state->crtc_h));
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/* Set base coordinates */
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DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
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state->crtc_x, state->crtc_y);
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regmap_write(backend->regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
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SUN4I_BACKEND_LAYCOOR(state->crtc_x,
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state->crtc_y));
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return 0;
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}
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EXPORT_SYMBOL(sun4i_backend_update_layer_coord);
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int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
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int layer, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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bool interlaced = false;
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u32 val;
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int ret;
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if (plane->state->crtc)
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interlaced = plane->state->crtc->state->adjusted_mode.flags
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& DRM_MODE_FLAG_INTERLACE;
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regmap_update_bits(backend->regs, SUN4I_BACKEND_MODCTL_REG,
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SUN4I_BACKEND_MODCTL_ITLMOD_EN,
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interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
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DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
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interlaced ? "on" : "off");
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ret = sun4i_backend_drm_format_to_layer(plane, fb->format->format,
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&val);
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if (ret) {
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DRM_DEBUG_DRIVER("Invalid format\n");
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return ret;
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}
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regmap_update_bits(backend->regs, SUN4I_BACKEND_ATTCTL_REG1(layer),
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SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
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return 0;
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}
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EXPORT_SYMBOL(sun4i_backend_update_layer_formats);
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int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
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int layer, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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struct drm_gem_cma_object *gem;
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u32 lo_paddr, hi_paddr;
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dma_addr_t paddr;
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int bpp;
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/* Get the physical address of the buffer in memory */
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
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/* Compute the start of the displayed memory */
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bpp = fb->format->cpp[0];
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paddr = gem->paddr + fb->offsets[0];
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paddr += (state->src_x >> 16) * bpp;
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paddr += (state->src_y >> 16) * fb->pitches[0];
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DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
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/* Write the 32 lower bits of the address (in bits) */
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lo_paddr = paddr << 3;
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DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
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regmap_write(backend->regs, SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
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lo_paddr);
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/* And the upper bits */
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hi_paddr = paddr >> 29;
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DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
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regmap_update_bits(backend->regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
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SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
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SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
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return 0;
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}
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EXPORT_SYMBOL(sun4i_backend_update_layer_buffer);
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static int sun4i_backend_init_sat(struct device *dev) {
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struct sun4i_backend *backend = dev_get_drvdata(dev);
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int ret;
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backend->sat_reset = devm_reset_control_get(dev, "sat");
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if (IS_ERR(backend->sat_reset)) {
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dev_err(dev, "Couldn't get the SAT reset line\n");
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return PTR_ERR(backend->sat_reset);
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}
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ret = reset_control_deassert(backend->sat_reset);
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if (ret) {
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dev_err(dev, "Couldn't deassert the SAT reset line\n");
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return ret;
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}
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backend->sat_clk = devm_clk_get(dev, "sat");
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if (IS_ERR(backend->sat_clk)) {
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dev_err(dev, "Couldn't get our SAT clock\n");
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ret = PTR_ERR(backend->sat_clk);
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goto err_assert_reset;
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}
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ret = clk_prepare_enable(backend->sat_clk);
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if (ret) {
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dev_err(dev, "Couldn't enable the SAT clock\n");
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return ret;
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}
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return 0;
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err_assert_reset:
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reset_control_assert(backend->sat_reset);
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return ret;
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}
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static int sun4i_backend_free_sat(struct device *dev) {
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struct sun4i_backend *backend = dev_get_drvdata(dev);
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clk_disable_unprepare(backend->sat_clk);
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reset_control_assert(backend->sat_reset);
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return 0;
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}
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static struct regmap_config sun4i_backend_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x5800,
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};
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static int sun4i_backend_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct drm_device *drm = data;
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struct sun4i_drv *drv = drm->dev_private;
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struct sun4i_backend *backend;
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struct resource *res;
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void __iomem *regs;
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int i, ret;
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backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
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if (!backend)
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return -ENOMEM;
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dev_set_drvdata(dev, backend);
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drv->backend = backend;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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backend->regs = devm_regmap_init_mmio(dev, regs,
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&sun4i_backend_regmap_config);
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if (IS_ERR(backend->regs)) {
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dev_err(dev, "Couldn't create the backend0 regmap\n");
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return PTR_ERR(backend->regs);
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}
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backend->reset = devm_reset_control_get(dev, NULL);
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if (IS_ERR(backend->reset)) {
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dev_err(dev, "Couldn't get our reset line\n");
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return PTR_ERR(backend->reset);
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}
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ret = reset_control_deassert(backend->reset);
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if (ret) {
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dev_err(dev, "Couldn't deassert our reset line\n");
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return ret;
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}
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backend->bus_clk = devm_clk_get(dev, "ahb");
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if (IS_ERR(backend->bus_clk)) {
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dev_err(dev, "Couldn't get the backend bus clock\n");
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ret = PTR_ERR(backend->bus_clk);
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goto err_assert_reset;
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}
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clk_prepare_enable(backend->bus_clk);
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backend->mod_clk = devm_clk_get(dev, "mod");
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if (IS_ERR(backend->mod_clk)) {
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dev_err(dev, "Couldn't get the backend module clock\n");
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ret = PTR_ERR(backend->mod_clk);
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goto err_disable_bus_clk;
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}
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clk_prepare_enable(backend->mod_clk);
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backend->ram_clk = devm_clk_get(dev, "ram");
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if (IS_ERR(backend->ram_clk)) {
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dev_err(dev, "Couldn't get the backend RAM clock\n");
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ret = PTR_ERR(backend->ram_clk);
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goto err_disable_mod_clk;
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}
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clk_prepare_enable(backend->ram_clk);
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if (of_device_is_compatible(dev->of_node,
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"allwinner,sun8i-a33-display-backend")) {
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ret = sun4i_backend_init_sat(dev);
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if (ret) {
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dev_err(dev, "Couldn't init SAT resources\n");
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goto err_disable_ram_clk;
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}
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}
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/* Reset the registers */
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for (i = 0x800; i < 0x1000; i += 4)
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regmap_write(backend->regs, i, 0);
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/* Disable registers autoloading */
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regmap_write(backend->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
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SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
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/* Enable the backend */
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regmap_write(backend->regs, SUN4I_BACKEND_MODCTL_REG,
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SUN4I_BACKEND_MODCTL_DEBE_EN |
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SUN4I_BACKEND_MODCTL_START_CTL);
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return 0;
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err_disable_ram_clk:
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clk_disable_unprepare(backend->ram_clk);
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err_disable_mod_clk:
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clk_disable_unprepare(backend->mod_clk);
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err_disable_bus_clk:
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clk_disable_unprepare(backend->bus_clk);
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err_assert_reset:
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reset_control_assert(backend->reset);
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return ret;
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}
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static void sun4i_backend_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct sun4i_backend *backend = dev_get_drvdata(dev);
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if (of_device_is_compatible(dev->of_node,
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"allwinner,sun8i-a33-display-backend"))
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sun4i_backend_free_sat(dev);
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clk_disable_unprepare(backend->ram_clk);
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clk_disable_unprepare(backend->mod_clk);
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clk_disable_unprepare(backend->bus_clk);
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reset_control_assert(backend->reset);
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}
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static const struct component_ops sun4i_backend_ops = {
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.bind = sun4i_backend_bind,
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.unbind = sun4i_backend_unbind,
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};
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static int sun4i_backend_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &sun4i_backend_ops);
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}
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static int sun4i_backend_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &sun4i_backend_ops);
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return 0;
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}
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static const struct of_device_id sun4i_backend_of_table[] = {
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{ .compatible = "allwinner,sun5i-a13-display-backend" },
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{ .compatible = "allwinner,sun6i-a31-display-backend" },
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{ .compatible = "allwinner,sun8i-a33-display-backend" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
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static struct platform_driver sun4i_backend_platform_driver = {
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.probe = sun4i_backend_probe,
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.remove = sun4i_backend_remove,
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.driver = {
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.name = "sun4i-backend",
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.of_match_table = sun4i_backend_of_table,
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},
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};
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module_platform_driver(sun4i_backend_platform_driver);
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MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
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MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
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MODULE_LICENSE("GPL");
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