697 lines
19 KiB
C
697 lines
19 KiB
C
/*
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* Broadcom BCM7xxx internal transceivers support.
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*
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* Copyright (C) 2014-2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include "bcm-phy-lib.h"
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#include <linux/bitops.h>
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#include <linux/brcmphy.h>
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#include <linux/mdio.h>
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/* Broadcom BCM7xxx internal PHY registers */
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/* EPHY only register definitions */
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#define MII_BCM7XXX_100TX_AUX_CTL 0x10
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#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
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#define MII_BCM7XXX_100TX_DISC 0x14
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#define MII_BCM7XXX_AUX_MODE 0x1d
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#define MII_BCM7XXX_64CLK_MDIO BIT(12)
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#define MII_BCM7XXX_TEST 0x1f
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#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
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#define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
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#define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
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#define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
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#define MII_BCM7XXX_SHD_3_AN_EEE_ADV 0x3
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#define MII_BCM7XXX_SHD_3_PCS_CTRL_2 0x6
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#define MII_BCM7XXX_PCS_CTRL_2_DEF 0x4400
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#define MII_BCM7XXX_SHD_3_AN_STAT 0xb
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#define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0)
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#define MII_BCM7XXX_AN_EEE_EN BIT(1)
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#define MII_BCM7XXX_SHD_3_EEE_THRESH 0xe
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#define MII_BCM7XXX_EEE_THRESH_DEF 0x50
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#define MII_BCM7XXX_SHD_3_TL4 0x23
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#define MII_BCM7XXX_TL4_RST_MSK (BIT(2) | BIT(1))
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/* 28nm only register definitions */
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#define MISC_ADDR(base, channel) base, channel
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#define DSP_TAP10 MISC_ADDR(0x0a, 0)
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#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
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#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
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#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
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#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
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#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
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#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
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#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
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#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
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#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
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#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
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#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
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struct bcm7xxx_phy_priv {
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u64 *stats;
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};
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static void r_rc_cal_reset(struct phy_device *phydev)
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{
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/* Reset R_CAL/RC_CAL Engine */
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bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010);
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/* Disable Reset R_AL/RC_CAL Engine */
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bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000);
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}
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static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
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{
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/* Increase VCO range to prevent unlocking problem of PLL at low
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* temp
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*/
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bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
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/* Change Ki to 011 */
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bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
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/* Disable loading of TVCO buffer to bandgap, set bandgap trim
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* to 111
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*/
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bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
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/* Adjust bias current trim by -3 */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
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/* Switch to CORE_BASE1E */
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phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
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r_rc_cal_reset(phydev);
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/* write AFE_RXCONFIG_0 */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
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/* write AFE_RXCONFIG_1 */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
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/* write AFE_RX_LP_COUNTER */
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bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
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/* write AFE_HPF_TRIM_OTHERS */
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
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/* write AFTE_TX_CONFIG */
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bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
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return 0;
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}
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static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
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{
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/* AFE_RXCONFIG_0 */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
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/* AFE_RXCONFIG_1 */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
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/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
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/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
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bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
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/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
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bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
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/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
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bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
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/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
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bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
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/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
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* offset for HT=0 code
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*/
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
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/* Reset R_CAL/RC_CAL engine */
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r_rc_cal_reset(phydev);
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return 0;
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}
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static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
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{
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/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
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/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
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bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
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/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
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bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
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/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
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* offset for HT=0 code
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*/
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
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/* Reset R_CAL/RC_CAL engine */
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r_rc_cal_reset(phydev);
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return 0;
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}
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static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
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{
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/* +1 RC_CAL codes for RL centering for both LT and HT conditions */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
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/* Cut master bias current by 2% to compensate for RC_CAL offset */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
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/* Improve hybrid leakage */
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
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/* Change rx_on_tune 8 to 0xf */
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bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
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/* Change 100Tx EEE bandwidth */
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bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
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/* Enable ffe zero detection for Vitesse interoperability */
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bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
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r_rc_cal_reset(phydev);
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return 0;
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}
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static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
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{
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u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
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u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
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u8 count;
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int ret = 0;
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/* Newer devices have moved the revision information back into a
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* standard location in MII_PHYS_ID[23]
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*/
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if (rev == 0)
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rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
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pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
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phydev_name(phydev), phydev->drv->name, rev, patch);
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/* Dummy read to a register to workaround an issue upon reset where the
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* internal inverter may not allow the first MDIO transaction to pass
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* the MDIO management controller and make us return 0xffff for such
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* reads.
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*/
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phy_read(phydev, MII_BMSR);
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switch (rev) {
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case 0xa0:
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case 0xb0:
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ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
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break;
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case 0xd0:
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ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
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break;
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case 0xe0:
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case 0xf0:
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/* Rev G0 introduces a roll over */
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case 0x10:
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ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
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break;
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case 0x01:
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ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
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break;
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default:
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break;
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}
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if (ret)
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return ret;
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ret = bcm_phy_downshift_get(phydev, &count);
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if (ret)
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return ret;
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/* Only enable EEE if Wirespeed/downshift is disabled */
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ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
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if (ret)
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return ret;
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return bcm_phy_enable_apd(phydev, true);
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}
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static int bcm7xxx_28nm_resume(struct phy_device *phydev)
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{
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int ret;
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/* Re-apply workarounds coming out suspend/resume */
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ret = bcm7xxx_28nm_config_init(phydev);
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if (ret)
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return ret;
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/* 28nm Gigabit PHYs come out of reset without any half-duplex
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* or "hub" compliant advertised mode, fix that. This does not
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* cause any problems with the PHY library since genphy_config_aneg()
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* gracefully handles auto-negotiated and forced modes.
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*/
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return genphy_config_aneg(phydev);
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}
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static int phy_set_clr_bits(struct phy_device *dev, int location,
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int set_mask, int clr_mask)
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{
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int v, ret;
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v = phy_read(dev, location);
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if (v < 0)
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return v;
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v &= ~clr_mask;
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v |= set_mask;
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ret = phy_write(dev, location, v);
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if (ret < 0)
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return ret;
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return v;
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}
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static int bcm7xxx_28nm_ephy_01_afe_config_init(struct phy_device *phydev)
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{
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int ret;
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/* set shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
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MII_BCM7XXX_SHD_MODE_2, 0);
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if (ret < 0)
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return ret;
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/* Set current trim values INT_trim = -1, Ext_trim =0 */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
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if (ret < 0)
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goto reset_shadow_mode;
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/* Cal reset */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_TL4);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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MII_BCM7XXX_TL4_RST_MSK, 0);
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if (ret < 0)
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goto reset_shadow_mode;
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/* Cal reset disable */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_TL4);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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0, MII_BCM7XXX_TL4_RST_MSK);
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if (ret < 0)
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goto reset_shadow_mode;
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reset_shadow_mode:
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/* reset shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
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MII_BCM7XXX_SHD_MODE_2);
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if (ret < 0)
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return ret;
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return 0;
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}
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/* The 28nm EPHY does not support Clause 45 (MMD) used by bcm-phy-lib */
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static int bcm7xxx_28nm_ephy_apd_enable(struct phy_device *phydev)
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{
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int ret;
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/* set shadow mode 1 */
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ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST,
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MII_BRCM_FET_BT_SRE, 0);
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if (ret < 0)
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return ret;
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/* Enable auto-power down */
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ret = phy_set_clr_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
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MII_BRCM_FET_SHDW_AS2_APDE, 0);
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if (ret < 0)
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return ret;
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/* reset shadow mode 1 */
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ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0,
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MII_BRCM_FET_BT_SRE);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int bcm7xxx_28nm_ephy_eee_enable(struct phy_device *phydev)
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{
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int ret;
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/* set shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
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MII_BCM7XXX_SHD_MODE_2, 0);
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if (ret < 0)
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return ret;
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/* Advertise supported modes */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_AN_EEE_ADV);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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MDIO_EEE_100TX);
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if (ret < 0)
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goto reset_shadow_mode;
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/* Restore Defaults */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_PCS_CTRL_2);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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MII_BCM7XXX_PCS_CTRL_2_DEF);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_EEE_THRESH);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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MII_BCM7XXX_EEE_THRESH_DEF);
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if (ret < 0)
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goto reset_shadow_mode;
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/* Enable EEE autonegotiation */
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
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MII_BCM7XXX_SHD_3_AN_STAT);
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if (ret < 0)
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goto reset_shadow_mode;
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ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
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(MII_BCM7XXX_AN_NULL_MSG_EN | MII_BCM7XXX_AN_EEE_EN));
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if (ret < 0)
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goto reset_shadow_mode;
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reset_shadow_mode:
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/* reset shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0,
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MII_BCM7XXX_SHD_MODE_2);
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if (ret < 0)
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return ret;
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/* Restart autoneg */
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phy_write(phydev, MII_BMCR,
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(BMCR_SPEED100 | BMCR_ANENABLE | BMCR_ANRESTART));
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return 0;
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}
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static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
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{
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u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
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int ret = 0;
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pr_info_once("%s: %s PHY revision: 0x%02x\n",
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phydev_name(phydev), phydev->drv->name, rev);
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/* Dummy read to a register to workaround a possible issue upon reset
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* where the internal inverter may not allow the first MDIO transaction
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* to pass the MDIO management controller and make us return 0xffff for
|
|
* such reads.
|
|
*/
|
|
phy_read(phydev, MII_BMSR);
|
|
|
|
/* Apply AFE software work-around if necessary */
|
|
if (rev == 0x01) {
|
|
ret = bcm7xxx_28nm_ephy_01_afe_config_init(phydev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = bcm7xxx_28nm_ephy_eee_enable(phydev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return bcm7xxx_28nm_ephy_apd_enable(phydev);
|
|
}
|
|
|
|
static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
/* Re-apply workarounds coming out suspend/resume */
|
|
ret = bcm7xxx_28nm_ephy_config_init(phydev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return genphy_config_aneg(phydev);
|
|
}
|
|
|
|
static int bcm7xxx_config_init(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
/* Enable 64 clock MDIO */
|
|
phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
|
|
phy_read(phydev, MII_BCM7XXX_AUX_MODE);
|
|
|
|
/* set shadow mode 2 */
|
|
ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
|
|
MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* set iddq_clkbias */
|
|
phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
|
|
udelay(10);
|
|
|
|
/* reset iddq_clkbias */
|
|
phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
|
|
|
|
phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
|
|
|
|
/* reset shadow mode 2 */
|
|
ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Workaround for putting the PHY in IDDQ mode, required
|
|
* for all BCM7XXX 40nm and 65nm PHYs
|
|
*/
|
|
static int bcm7xxx_suspend(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
static const struct bcm7xxx_regs {
|
|
int reg;
|
|
u16 value;
|
|
} bcm7xxx_suspend_cfg[] = {
|
|
{ MII_BCM7XXX_TEST, 0x008b },
|
|
{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
|
|
{ MII_BCM7XXX_100TX_DISC, 0x7000 },
|
|
{ MII_BCM7XXX_TEST, 0x000f },
|
|
{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
|
|
{ MII_BCM7XXX_TEST, 0x000b },
|
|
};
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
|
|
ret = phy_write(phydev,
|
|
bcm7xxx_suspend_cfg[i].reg,
|
|
bcm7xxx_suspend_cfg[i].value);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
|
|
struct ethtool_tunable *tuna,
|
|
void *data)
|
|
{
|
|
switch (tuna->id) {
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
return bcm_phy_downshift_get(phydev, (u8 *)data);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
|
|
struct ethtool_tunable *tuna,
|
|
const void *data)
|
|
{
|
|
u8 count = *(u8 *)data;
|
|
int ret;
|
|
|
|
switch (tuna->id) {
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
ret = bcm_phy_downshift_set(phydev, count);
|
|
break;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Disable EEE advertisement since this prevents the PHY
|
|
* from successfully linking up, trigger auto-negotiation restart
|
|
* to let the MAC decide what to do.
|
|
*/
|
|
ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return genphy_restart_aneg(phydev);
|
|
}
|
|
|
|
static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
|
|
struct ethtool_stats *stats, u64 *data)
|
|
{
|
|
struct bcm7xxx_phy_priv *priv = phydev->priv;
|
|
|
|
bcm_phy_get_stats(phydev, priv->stats, stats, data);
|
|
}
|
|
|
|
static int bcm7xxx_28nm_probe(struct phy_device *phydev)
|
|
{
|
|
struct bcm7xxx_phy_priv *priv;
|
|
|
|
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
phydev->priv = priv;
|
|
|
|
priv->stats = devm_kcalloc(&phydev->mdio.dev,
|
|
bcm_phy_get_sset_count(phydev), sizeof(u64),
|
|
GFP_KERNEL);
|
|
if (!priv->stats)
|
|
return -ENOMEM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define BCM7XXX_28NM_GPHY(_oui, _name) \
|
|
{ \
|
|
.phy_id = (_oui), \
|
|
.phy_id_mask = 0xfffffff0, \
|
|
.name = _name, \
|
|
.features = PHY_GBIT_FEATURES, \
|
|
.flags = PHY_IS_INTERNAL, \
|
|
.config_init = bcm7xxx_28nm_config_init, \
|
|
.resume = bcm7xxx_28nm_resume, \
|
|
.get_tunable = bcm7xxx_28nm_get_tunable, \
|
|
.set_tunable = bcm7xxx_28nm_set_tunable, \
|
|
.get_sset_count = bcm_phy_get_sset_count, \
|
|
.get_strings = bcm_phy_get_strings, \
|
|
.get_stats = bcm7xxx_28nm_get_phy_stats, \
|
|
.probe = bcm7xxx_28nm_probe, \
|
|
}
|
|
|
|
#define BCM7XXX_28NM_EPHY(_oui, _name) \
|
|
{ \
|
|
.phy_id = (_oui), \
|
|
.phy_id_mask = 0xfffffff0, \
|
|
.name = _name, \
|
|
.features = PHY_BASIC_FEATURES, \
|
|
.flags = PHY_IS_INTERNAL, \
|
|
.config_init = bcm7xxx_28nm_ephy_config_init, \
|
|
.resume = bcm7xxx_28nm_ephy_resume, \
|
|
.get_sset_count = bcm_phy_get_sset_count, \
|
|
.get_strings = bcm_phy_get_strings, \
|
|
.get_stats = bcm7xxx_28nm_get_phy_stats, \
|
|
.probe = bcm7xxx_28nm_probe, \
|
|
}
|
|
|
|
#define BCM7XXX_40NM_EPHY(_oui, _name) \
|
|
{ \
|
|
.phy_id = (_oui), \
|
|
.phy_id_mask = 0xfffffff0, \
|
|
.name = _name, \
|
|
.features = PHY_BASIC_FEATURES, \
|
|
.flags = PHY_IS_INTERNAL, \
|
|
.config_init = bcm7xxx_config_init, \
|
|
.suspend = bcm7xxx_suspend, \
|
|
.resume = bcm7xxx_config_init, \
|
|
}
|
|
|
|
static struct phy_driver bcm7xxx_driver[] = {
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
|
|
BCM7XXX_28NM_EPHY(PHY_ID_BCM7260, "Broadcom BCM7260"),
|
|
BCM7XXX_28NM_EPHY(PHY_ID_BCM7268, "Broadcom BCM7268"),
|
|
BCM7XXX_28NM_EPHY(PHY_ID_BCM7271, "Broadcom BCM7271"),
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
|
|
BCM7XXX_28NM_GPHY(PHY_ID_BCM_OMEGA, "Broadcom Omega Combo GPHY"),
|
|
BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"),
|
|
BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"),
|
|
BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"),
|
|
BCM7XXX_40NM_EPHY(PHY_ID_BCM7429, "Broadcom BCM7429"),
|
|
BCM7XXX_40NM_EPHY(PHY_ID_BCM7435, "Broadcom BCM7435"),
|
|
};
|
|
|
|
static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
|
|
{ PHY_ID_BCM7250, 0xfffffff0, },
|
|
{ PHY_ID_BCM7260, 0xfffffff0, },
|
|
{ PHY_ID_BCM7268, 0xfffffff0, },
|
|
{ PHY_ID_BCM7271, 0xfffffff0, },
|
|
{ PHY_ID_BCM7278, 0xfffffff0, },
|
|
{ PHY_ID_BCM7364, 0xfffffff0, },
|
|
{ PHY_ID_BCM7366, 0xfffffff0, },
|
|
{ PHY_ID_BCM7346, 0xfffffff0, },
|
|
{ PHY_ID_BCM7362, 0xfffffff0, },
|
|
{ PHY_ID_BCM7425, 0xfffffff0, },
|
|
{ PHY_ID_BCM7429, 0xfffffff0, },
|
|
{ PHY_ID_BCM74371, 0xfffffff0, },
|
|
{ PHY_ID_BCM7439, 0xfffffff0, },
|
|
{ PHY_ID_BCM7435, 0xfffffff0, },
|
|
{ PHY_ID_BCM7445, 0xfffffff0, },
|
|
{ }
|
|
};
|
|
|
|
module_phy_driver(bcm7xxx_driver);
|
|
|
|
MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
|
|
|
|
MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Broadcom Corporation");
|