366 lines
10 KiB
C
366 lines
10 KiB
C
/*
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* HDMI CEC
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*
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* Based on the CEC code from hdmi_ti_4xxx_ip.c from Android.
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
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* Authors: Yong Zhi
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* Mythri pk <mythripk@ti.com>
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*
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* Heavily modified to use the linux CEC framework:
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*
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* Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "dss.h"
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#include "hdmi.h"
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#include "hdmi4_core.h"
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#include "hdmi4_cec.h"
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/* HDMI CEC */
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#define HDMI_CEC_DEV_ID 0x900
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#define HDMI_CEC_SPEC 0x904
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/* Not really a debug register, more a low-level control register */
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#define HDMI_CEC_DBG_3 0x91C
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#define HDMI_CEC_TX_INIT 0x920
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#define HDMI_CEC_TX_DEST 0x924
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#define HDMI_CEC_SETUP 0x938
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#define HDMI_CEC_TX_COMMAND 0x93C
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#define HDMI_CEC_TX_OPERAND 0x940
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#define HDMI_CEC_TRANSMIT_DATA 0x97C
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#define HDMI_CEC_CA_7_0 0x988
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#define HDMI_CEC_CA_15_8 0x98C
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#define HDMI_CEC_INT_STATUS_0 0x998
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#define HDMI_CEC_INT_STATUS_1 0x99C
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#define HDMI_CEC_INT_ENABLE_0 0x990
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#define HDMI_CEC_INT_ENABLE_1 0x994
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#define HDMI_CEC_RX_CONTROL 0x9B0
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#define HDMI_CEC_RX_COUNT 0x9B4
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#define HDMI_CEC_RX_CMD_HEADER 0x9B8
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#define HDMI_CEC_RX_COMMAND 0x9BC
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#define HDMI_CEC_RX_OPERAND 0x9C0
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#define HDMI_CEC_TX_FIFO_INT_MASK 0x64
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#define HDMI_CEC_RETRANSMIT_CNT_INT_MASK 0x2
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#define HDMI_CORE_CEC_RETRY 200
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static void hdmi_cec_received_msg(struct hdmi_core_data *core)
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{
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u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
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/* While there are CEC frames in the FIFO */
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while (cnt & 0x70) {
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/* and the frame doesn't have an error */
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if (!(cnt & 0x80)) {
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struct cec_msg msg = {};
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unsigned int i;
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/* then read the message */
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msg.len = cnt & 0xf;
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if (msg.len > CEC_MAX_MSG_SIZE - 2)
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msg.len = CEC_MAX_MSG_SIZE - 2;
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msg.msg[0] = hdmi_read_reg(core->base,
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HDMI_CEC_RX_CMD_HEADER);
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msg.msg[1] = hdmi_read_reg(core->base,
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HDMI_CEC_RX_COMMAND);
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for (i = 0; i < msg.len; i++) {
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unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4;
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msg.msg[2 + i] =
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hdmi_read_reg(core->base, reg);
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}
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msg.len += 2;
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cec_received_msg(core->adap, &msg);
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}
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/* Clear the current frame from the FIFO */
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hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1);
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/* Wait until the current frame is cleared */
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while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
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udelay(1);
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/*
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* Re-read the count register and loop to see if there are
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* more messages in the FIFO.
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*/
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cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
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}
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}
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void hdmi4_cec_irq(struct hdmi_core_data *core)
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{
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u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
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u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
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hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
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hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
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if (stat0 & 0x20) {
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cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
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0, 0, 0, 0);
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REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
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} else if (stat1 & 0x02) {
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u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
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cec_transmit_done(core->adap,
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CEC_TX_STATUS_NACK |
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CEC_TX_STATUS_MAX_RETRIES,
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0, (dbg3 >> 4) & 7, 0, 0);
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REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
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}
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if (stat0 & 0x02)
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hdmi_cec_received_msg(core);
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}
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static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
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{
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struct hdmi_core_data *core = cec_get_drvdata(adap);
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int retry = HDMI_CORE_CEC_RETRY;
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int temp;
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REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
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while (retry) {
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temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
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if (FLD_GET(temp, 7, 7) == 0)
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break;
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retry--;
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}
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return retry != 0;
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}
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static bool hdmi_cec_clear_rx_fifo(struct cec_adapter *adap)
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{
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struct hdmi_core_data *core = cec_get_drvdata(adap);
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int retry = HDMI_CORE_CEC_RETRY;
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int temp;
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hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3);
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retry = HDMI_CORE_CEC_RETRY;
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while (retry) {
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temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
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if (FLD_GET(temp, 1, 0) == 0)
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break;
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retry--;
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}
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return retry != 0;
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}
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static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
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{
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struct hdmi_core_data *core = cec_get_drvdata(adap);
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int temp, err;
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if (!enable) {
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hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0);
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hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0);
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REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
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hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
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hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
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REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
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hdmi4_core_disable(core);
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return 0;
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}
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err = hdmi4_core_enable(core);
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if (err)
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return err;
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/*
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* Initialize CEC clock divider: CEC needs 2MHz clock hence
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* set the divider to 24 to get 48/24=2MHz clock
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*/
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REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
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/* Clear TX FIFO */
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if (!hdmi_cec_clear_tx_fifo(adap)) {
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pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
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err = -EIO;
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goto err_disable_clk;
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}
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/* Clear RX FIFO */
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if (!hdmi_cec_clear_rx_fifo(adap)) {
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pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
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err = -EIO;
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goto err_disable_clk;
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}
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/* Clear CEC interrupts */
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hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
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hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
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hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
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hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));
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/* Enable HDMI core interrupts */
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hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE);
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/* Unmask CEC interrupt */
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REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3);
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/*
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* Enable CEC interrupts:
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* Transmit Buffer Full/Empty Change event
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* Receiver FIFO Not Empty event
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*/
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hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x22);
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/*
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* Enable CEC interrupts:
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* Frame Retransmit Count Exceeded event
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*/
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hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x02);
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/* cec calibration enable (self clearing) */
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hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
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msleep(20);
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hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04);
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temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
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if (FLD_GET(temp, 4, 4) != 0) {
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temp = FLD_MOD(temp, 0, 4, 4);
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hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp);
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/*
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* If we enabled CEC in middle of a CEC message on the bus,
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* we could have start bit irregularity and/or short
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* pulse event. Clear them now.
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*/
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temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
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temp = FLD_MOD(0x0, 0x5, 2, 0);
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hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
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}
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return 0;
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err_disable_clk:
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REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
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hdmi4_core_disable(core);
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return err;
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}
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static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
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{
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struct hdmi_core_data *core = cec_get_drvdata(adap);
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u32 v;
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if (log_addr == CEC_LOG_ADDR_INVALID) {
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hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0);
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hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0);
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return 0;
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}
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if (log_addr <= 7) {
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v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
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v |= 1 << log_addr;
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hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
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} else {
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v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
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v |= 1 << (log_addr - 8);
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hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
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}
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return 0;
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}
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static int hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
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u32 signal_free_time, struct cec_msg *msg)
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{
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struct hdmi_core_data *core = cec_get_drvdata(adap);
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int temp;
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u32 i;
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/* Clear TX FIFO */
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if (!hdmi_cec_clear_tx_fifo(adap)) {
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pr_err("cec-%s: could not clear TX FIFO for transmit\n",
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adap->name);
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return -EIO;
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}
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/* Clear TX interrupts */
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hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
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HDMI_CEC_TX_FIFO_INT_MASK);
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hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
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HDMI_CEC_RETRANSMIT_CNT_INT_MASK);
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/* Set the retry count */
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REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);
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/* Set the initiator addresses */
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hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg));
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/* Set destination id */
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temp = cec_msg_destination(msg);
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if (msg->len == 1)
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temp |= 0x80;
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hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp);
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if (msg->len == 1)
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return 0;
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/* Setup command and arguments for the command */
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hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]);
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for (i = 0; i < msg->len - 2; i++)
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hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4,
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msg->msg[2 + i]);
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/* Operand count */
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hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA,
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(msg->len - 2) | 0x10);
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return 0;
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}
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static const struct cec_adap_ops hdmi_cec_adap_ops = {
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.adap_enable = hdmi_cec_adap_enable,
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.adap_log_addr = hdmi_cec_adap_log_addr,
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.adap_transmit = hdmi_cec_adap_transmit,
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};
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void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
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{
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cec_s_phys_addr(core->adap, pa, false);
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}
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int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
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struct hdmi_wp_data *wp)
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{
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const u32 caps = CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
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CEC_CAP_PASSTHROUGH | CEC_CAP_RC;
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int ret;
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core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core,
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"omap4", caps, CEC_MAX_LOG_ADDRS);
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ret = PTR_ERR_OR_ZERO(core->adap);
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if (ret < 0)
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return ret;
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core->wp = wp;
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/* Disable clock initially, hdmi_cec_adap_enable() manages it */
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REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
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ret = cec_register_adapter(core->adap, &pdev->dev);
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if (ret < 0) {
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cec_delete_adapter(core->adap);
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return ret;
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}
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return 0;
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}
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void hdmi4_cec_uninit(struct hdmi_core_data *core)
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{
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cec_unregister_adapter(core->adap);
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}
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